FISH: Fast Instruction SyntHesis for Custom Processors

Abstract

Abstract-This paper presents Fast Instruction SyntHesis (FISH), a system that supports automatic generation of custom instruction processors from high-level application descriptions to enable fast design space exploration. FISH is based on novel methods for automatically adapting the instruction set to match an application in a high-level language such as C or C. FISH identifies custom instruction candidates using two approaches: 1) by enumerating maximal convex subgraphs of application data flow graphs and 2) by integer linear programming (ILP). The experiments, involving ten multimedia and cryptography benchmarks, show that our contributed algorithms are the fastest among the state-of-the-art techniques. In most cases, enumeration takes only milliseconds to execute. The longest enumeration run-time observed is less than six seconds. ILP is usually slower than enumeration, but provides us with a complementary solution technique. Both enumeration and ILP allow the use of multiple different merit functions in the evaluation of data-flow subgraphs. The experiments demonstrate that, using only modest additional hardware resources, up to 30-fold performance improvement can be obtained with respect to a single-issue base processor.

Way Stealing: A Unified Data Cache and Architecturally Visible Storage for Instruction Set Extensions

“…ISE identification algorithms search for an ISE that maximizes a merit function, M(C), where C is the set of assembly-level operations that are included in the ISE [8][9][10][11][12][13][14][15][16][17]. C has a software cost, S(C), which is the estimated latency of executing the operations comprising C in software, and a hardware cost, H(C), which is the estimated latency of executing the operations comprising C as an ISE.…”

“…Traditional ISEs communicate directly with the register file of the extensible processor [8][9][10][11][12][13][14][15][16][17]. A typical RISC processor's register file has two read ports and one write port.…”

“…Many compiler algorithms have been proposed over the past decade to automatically identify and synthesize ISEs from an application specified in a high-level language [8][9][10][11][12][13][14][15][16][17]. These algorithms can be extended to identify AVS-enhanced ISEs as described by Biswas et al [18].…”

Virtual Ways: Low-Cost Coherence for Instruction Set Extensions with Architecturally Visible Storage

“…Most of the work on customizable processors has focused on compiler algorithms to automatically identify and synthesize ISEs [Pozzi et al 2006;Verma et al 2010;Atasu et al 2012]. Any of these algorithms can be extended to identify AVS-enhanced ISEs [Biswas et al 2007] and can integrate the cost model described in this article into the merit function that guides the search.…”

Vulnerability Analysis for Custom Instructions

“…Customizing the instruction set of a base processor is emerging as a key design methodology in new extensible embedded processors exploiting both programmability and efficiency. In these methods the base processor is extended with custom functional units that provide application-specific instructions [1], [2], [3], [4]. Major concerns in the design of a customized embedded processor are computational performance, area efficiency, and limited productivity of the designers.…”