Fixed-Latency, Multi-Gigabit Serial Links With Xilinx FPGAs

Giordano, R.; Aloisio, A.

doi:10.1109/tns.2010.2101083

Cited by 73 publications

(41 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…in [5]. Besides, our design requires synchronous retransmission of the receiver link data from the master front-end to the slave boards as outlined in section 1.…”

Section: Constant Latency Linkmentioning

confidence: 99%

The ARAGORN front-end — FPGA based implementation of a time-to-digital converter

Büchele

Fischer

Herrmann

et al. 2016

2016 IEEE Nuclear Science Symposium, Medical Imaging Conference and Room-Temperature Semiconductor Detector Workshop (NSS/MIC/R

View full text Add to dashboard Cite

A: We present the ARAGORN front-end, a cost-optimized, high-density Time-to-Digital Converter platform. Four Xilinx Artix-7 FPGAs implement 384 channels with an average time resolution of 165 ps on a single module. A fifth FPGA acts as data concentrator and generic board master. The front-end features a SFP+ transceiver for data output and an optional multi-channel optical transceiver slot to interconnect with up to seven boards though a star topology. This novel approach makes it possible to read out up to eight boards yielding 3072 input channels via a single optical fiber at a bandwidth of 6.6 Gb/s.

show abstract

“…in [5]. Besides, our design requires synchronous retransmission of the receiver link data from the master front-end to the slave boards as outlined in section 1.…”

Section: Constant Latency Linkmentioning

confidence: 99%

The ARAGORN front-end — FPGA based implementation of a time-to-digital converter

Büchele

Fischer

Herrmann

et al. 2016

2016 IEEE Nuclear Science Symposium, Medical Imaging Conference and Room-Temperature Semiconductor Detector Workshop (NSS/MIC/R

View full text Add to dashboard Cite

show abstract

“…Deterministic-latency links [5][6][7][8] find also application in data acquisition systems of nuclear and sub-nuclear physics experiments, specifically in the trigger sub-systems, where it is crucial to preserve the timing information associated with the transferred signals.…”

Section: Introductionmentioning

confidence: 99%

High‐Speed Deterministic‐Latency Serial IO

Giordano¹,

Izzo²,

Aloisio³

2017

Field - Programmable Gate Array

Self Cite

View full text Add to dashboard Cite

In digital systems, serial IO at speeds in the range from 1 to 20 Gbps is realized by means of dedicated transceivers, named serializer-deserializers (SerDeses). In general, due to their internal architecture, the data transfer delay, or the latency, may vary after a reset of the device. On the other hand, some applications, such as high-speed transfer protocols for analog-to-digital and digital-to-analog converters, trigger and data acquisition systems, clock distribution, synchronization and control of radio equipment need this delay to be constant at each reset. In this chapter, we focus on a serial IO architecture based on configurable transceivers embedded in field-programmable gate arrays (FPGAs). We will show how it is possible to achieve deterministic-latency operation in a line-codeindependent way. As a case study, we will consider a synchronous 2.5-Gbps serial link based on an 8b10b line code.

show abstract

“…Needless to say, the successors to the Virtex-5 family remain compliant with deterministic latency. [336][337], with uncertainties in the elastic buffer at the transmitter and the word aligner at the receiver; the elastic FIFO at the receiver appears to be deterministic, as reported in [135] and confirmed in ( [102], p. 185) under stability conditions. In any case, both FIFOs may be bypassed as long as the device is configured in "TX phase alignment" and "RX phase alignment" mode, respectively, where GTP-generated parallel clocks are automatically phase-shifted in order to remove the need for adaptation stages.…”

Section: -93) Virtex-4 Devices Included Mgtsmentioning

confidence: 57%

“…However, the most popular platform for the implementation of deterministic latency links seems to be the Virtex-5 with embedded GTP/GTX transceivers [102], which has been evaluated extensively in the available literature [74,[135][136][137][138]. Needless to say, the successors to the Virtex-5 family remain compliant with deterministic latency.…”

Section: -93) Virtex-4 Devices Included Mgtsmentioning

confidence: 99%

See 1 more Smart Citation

Development of a data acquisition architecture with distributed synchronization for a Positron Emission Tomography system with integrated front-end.

Varea¹,

Ramón²

View full text Add to dashboard Cite

Positron Emission Tomography (PET) is a non-invasive nuclear medical imaging modality that makes it possible to observe the distribution of metabolic substances within a patient's body after marking them with radioactive isotopes and arranging an annular scanner around him in order to detect their decays. The main applications of this technique are the detection and tracing of tumors in cancer patients and metabolic studies with small animals.The Electronic Design for Nuclear Applications (EDNA) research group within the Instituto de Instrumentación para Imagen Molecular (I3M) has been involved in the study of high performance PET systems and maintains a small experimental setup with two detector modules. This thesis is framed within the necessity of developing a new data acquisition system (DAQ) for the aforementioned setup that corrects the drawbacks of the existing one. The main objective is to define a DAQ architecture that is completely scalable, modular, and guarantees the mobility and the possibility of reusing its components, so that it admits any extension of modification of the setup and it is possible to export it directly to the configurations used by other groups or experiments. At the same time, this architecture should be compatible with the best possible resolutions attainable at the present instead of imposing artificial limits on system performance. In particular, the new DAQ system should outperform the previous one.As a first step, a general study of DAQ architectures is carried out in the context of experimental setups for PET and other high energy physics applications. On one hand, the conclusion is reached that the desired specifications require early digitization of detector signals, exclusively digital communication between modules, and the absence of a centralized trigger. On the other hand, the necessity of a very precise distributed synchronization scheme between modules becomes apparent, with errors in the order of 100 ps, and operating directly over the data links. A study of the existing methods reveals their severe limitations in terms of achievable precision. A theoretical analysis of the situation is carried out with the goal of overcoming them, and a new synchronization algorithm is proposed that is able to reach the desired resolution while getting rid of the restrictions on clock iii alignment that are imposed by virtually all usual schemes. Since the measurement of clock phase difference plays a crucial role in the proposed algorithm, extensions to the existing methods are defined and analyzed that improve them significantly. The proposed scheme for synchronism is validated using commercial evaluation boards.Taking the proposed synchronization method as a starting point, a DAQ architecture for PET is defined that is composed of two types of module (acquisition and concentration) whose replication makes it possible to arrange a hierarchic system of arbitrary size, and circuit boards are designed and commissioned that implement a realization of the architecture for the...

show abstract

Fixed-Latency, Multi-Gigabit Serial Links With Xilinx FPGAs

Cited by 73 publications

References 9 publications

The ARAGORN front-end — FPGA based implementation of a time-to-digital converter

The ARAGORN front-end — FPGA based implementation of a time-to-digital converter

High‐Speed Deterministic‐Latency Serial IO

Development of a data acquisition architecture with distributed synchronization for a Positron Emission Tomography system with integrated front-end.

Contact Info

Product

Resources

About