2016 IEEE Nuclear Science Symposium, Medical Imaging Conference and Room-Temperature Semiconductor Detector Workshop (NSS/MIC/R 2016
DOI: 10.1109/nssmic.2016.8069886
|View full text |Cite
|
Sign up to set email alerts
|

The ARAGORN front-end — FPGA based implementation of a time-to-digital converter

Abstract: A: We present the ARAGORN front-end, a cost-optimized, high-density Time-to-Digital Converter platform. Four Xilinx Artix-7 FPGAs implement 384 channels with an average time resolution of 165 ps on a single module. A fifth FPGA acts as data concentrator and generic board master. The front-end features a SFP+ transceiver for data output and an optional multi-channel optical transceiver slot to interconnect with up to seven boards though a star topology. This novel approach makes it possible to read out up to ei… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...

Citation Types

0
0
0

Year Published

2019
2019
2019
2019

Publication Types

Select...
1

Relationship

0
1

Authors

Journals

citations
Cited by 1 publication
references
References 1 publication
0
0
0
Order By: Relevance