Recent Developments and Challenges in FPGA-Based Time-to-Digital Converters

Machado, Rui; Cabral, Jorge; Alves, Filipe

doi:10.1109/tim.2019.2938436

Cited by 93 publications

(45 citation statements)

References 135 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…TDC nonlinearities would directly affect the resolution of the system. The most commonly-used metrics to characterize TDC nonlinearities are differential nonlinearity (DNL) and integral nonlinearity (INL) [31,32]. DNL describes the difference between each bin width and the ideal bin width, which is also known as the least significant bit (LSB) and reflects the degree of nonlinearity of single bin width.…”

Section: Nonlinearitiesmentioning

confidence: 99%

An 8.8 ps RMS Resolution Time-To-Digital Converter Implemented in a 60 nm FPGA with Real-Time Temperature Correction

Song

Zhao

et al. 2020

Sensors

View full text Add to dashboard Cite

This paper presented a non-uniform multiphase (NUMP) time-to-digital converter (TDC) implemented in a field-programmable gate array (FPGA) with real-time automatic temperature compensation. NUMP-TDC is a novel, low-cost, high-performance TDC that has achieved an excellent performance in Altera Cyclone V FPGA. The root mean square (RMS) for the intrinsic timing resolution was 2.3 ps. However, the propagation delays in the delay chain of some FPGAs (for example, the Altera Cyclone 10 LP) vary significantly as the temperature changes. Thus, the timing performances of NUMP-TDCs implemented in those FPGAs are significantly impacted by temperature fluctuations. In this study, a simple method was developed to monitor variations in propagation delays using two registers deployed at both ends of the delay chain and compensate for changes in propagation delay using a look-up table (LUT). When the variations exceeded a certain threshold, the LUT for the delay correction was updated, and a bin-by-bin correction was launched. Using this correction approach, a resolution of 8.8 ps RMS over a wide temperature range (5 °C to 80 °C) had been achieved in a NUMP-TDC implemented in a Cyclone 10 LP FPGA.

show abstract

Section: Nonlinearitiesmentioning

confidence: 99%

An 8.8 ps RMS Resolution Time-To-Digital Converter Implemented in a 60 nm FPGA with Real-Time Temperature Correction

Song

Zhao

et al. 2020

Sensors

View full text Add to dashboard Cite

show abstract

“…The resolution or the least significant bit (LSB) is the least time interval a TDC can measure. The linearity can be characterized by the differential nonlinearity (DNL) and the integral nonlinearity (INL) [22]. The DNL is the deviation of a single quantization step from its ideal value, whereas the INL is the W. Xie, Y. Wang, H. Chen, and D. D.-U.…”

Section: Introductionmentioning

confidence: 99%

128-Channel High-Linearity Resolution-Adjustable Time-to-Digital Converters for LiDAR Applications: Software Predictions and Hardware Implementations

Xie

Wang

Chen

et al. 2022

IEEE Trans. Ind. Electron.

View full text Add to dashboard Cite

This paper proposes a new calibration method, called the mixed-binning (MB) method, to pursue highlinearity time-to-digital converters (TDCs) for light detection and ranging (LiDAR) applications. The proposed TDCs were developed using tapped delay-line (TDL) cells in fieldprogrammable gate arrays (FPGAs). With the MB method, we implemented a resolution-adjustable TDC showing excellent linearity in Xilinx UltraScale FPGAs. We demonstrate a 128-channel TDC to show that the proposed method is cost-effective in logic resources. We also developed a software tool to predict the performances of TDL-based TDCs robustly. Results from both software analysis and hardware implementations are in good agreement and show that the proposed design has great potential for multichannel applications; the averaged − and − are close to or even less than 0.05 LSB in multichannel designs. Index Terms-Light detection and ranging (LiDAR), Timeto-digital converters (TDCs), Time-of-flight (ToF), Fieldprogrammable gate arrays (FPGAs)

show abstract

“…In recent years, Field-Programmable Gate Arrays (FPGAs) have been considered as an interesting implementation platform for fully-digital TDCs because of their flexibility, faster development phase, and lower implementation cost than Application-Specific Integrated Circuits (ASICs). Additionally, FPGA’s carry elements, whose intrinsic propagation delays can be used as a sort of fine time interpolator, have made FPGAs a suitable solution to implement high-resolution TDCs [ 8 , 9 ].…”

Section: Introductionmentioning

confidence: 99%

“…Different techniques for implementing TDCs on FPGA have been introduced in recent years [ 9 , 10 ], depending on the application’s specific requirements. Seeking to expand the measurable time interval and achieve higher time resolutions, the Nutt method, which combines a coarse counter and a time interpolator, is the most extended technique in FPGA-based TDCs [ 11 , 12 ].…”

Section: Introductionmentioning

confidence: 99%

A Low-Resources TDC for Multi-Channel Direct ToF Readout Based on a 28-nm FPGA

Parsakordasiabi

Vornicu

Rodríguez-Vázquez

et al. 2021

Sensors

View full text Add to dashboard Cite

In this paper, we present a proposed field programmable gate array (FPGA)-based time-to-digital converter (TDC) architecture to achieve high performance with low usage of resources. This TDC can be employed for multi-channel direct Time-of-Flight (ToF) applications. The proposed architecture consists of a synchronizing input stage, a tuned tapped delay line (TDL), a combinatory encoder of ones and zeros counters, and an online calibration stage. The experimental results of the TDC in an Artix-7 FPGA show a differential non-linearity (DNL) in the range of [−0.953, 1.185] LSB, and an integral non-linearity (INL) within [−2.750, 1.238] LSB. The measured LSB size and precision are 22.2 ps and 26.04 ps, respectively. Moreover, the proposed architecture requires low FPGA resources.

show abstract

Recent Developments and Challenges in FPGA-Based Time-to-Digital Converters

Cited by 93 publications

References 135 publications

An 8.8 ps RMS Resolution Time-To-Digital Converter Implemented in a 60 nm FPGA with Real-Time Temperature Correction

An 8.8 ps RMS Resolution Time-To-Digital Converter Implemented in a 60 nm FPGA with Real-Time Temperature Correction

128-Channel High-Linearity Resolution-Adjustable Time-to-Digital Converters for LiDAR Applications: Software Predictions and Hardware Implementations

A Low-Resources TDC for Multi-Channel Direct ToF Readout Based on a 28-nm FPGA

Contact Info

Product

Resources

About