Fixed-Point Convolutional Neural Network for Real-Time Video Processing in FPGA

Solovyev, Roman; Kustov, A.G.; Telpukhov, Dmitry; Rukhlov, V. S.; Kalinin, Alexandr A.

doi:10.1109/eiconrus.2019.8656778

Cited by 18 publications

(5 citation statements)

References 7 publications

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“…The arithmetics can be divided into two big groups: fixed-point and floating-point. Fixed-point provides an optimal approach in FPGAs, minimizing area and maximizing speed, so many examples in the literature use it [1][2][3][4][5][6]. However, floating-point provides a bigger dynamic range, adapting the point location as it is required.…”

Section: Introductionmentioning

confidence: 99%

LOCOFloat: A Low-Cost Floating-Point Format for FPGAs.: Application to HIL Simulators

et al. 2020

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One of the main decisions when making a digital design is which arithmetic is going to be used. The arithmetic determines the hardware resources needed and the latency of every operation. This is especially important in real-time applications like HIL (Hardware-in-the-loop), where a real-time simulation of a plant—power converter, mechanical system, or any other complex system—is accomplished. While a fixed-point gets optimal implementations, using considerably fewer resources and allowing smaller simulation steps, its use is very restricted to very specific applications, as its design effort is quite high. On the other side, IEEE-754 floating-point may have resolution problems in case of the 32-bit version, and excessive hardware usage in case of the 64-bit version. This paper presents LOCOFloat, a low-cost floating-point format designed for FPGA applications. Its key features are soft normalization of the results, using significand and exponent fields in two’s complement. This paper shows the implementation of addition, subtraction and multiplication of the proposed format. Both IEEE-754 versions and LOCOFloat are compared in this paper, implementing a HIL model of a buck converter. Although the application example is a HIL simulator, other applications could take benefit from the proposed format. Results show that LOCOFloat is as accurate as 64-bit floating-point, while reducing the use of DSPs blocks by 84 % .

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Section: Introductionmentioning

confidence: 99%

LOCOFloat: A Low-Cost Floating-Point Format for FPGAs.: Application to HIL Simulators

et al. 2020

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“…In this work, we have concentrated only on VGG-based Low-Weight Digit Detector (LWDD) CNN system architecture, which is deployed in real-time handwritten digit recognition applications to detect digits from 0 to 9 [ 37 ].…”

Section: Convolutional Neural Network Accelerator For the Handwritten...mentioning

confidence: 99%

Power and Area Efficient Cascaded Effectless GDI Approximate Adder for Accelerating Multimedia Applications Using Deep Learning Model

Nagarajan

Muthaiah

Teekaraman

et al. 2022

Computational Intelligence and Neuroscience

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Approximate computing is an upsurging technique to accelerate the process through less computational effort while keeping admissible accuracy of error-tolerant applications such as multimedia and deep learning. Inheritance properties of the deep learning process aid the designer to abridge the circuitry and also to increase the computation speed at the cost of the accuracy of results. High computational complexity and low-power requirement of portable devices in the dark silicon era sought suitable alternate for Complementary Metal Oxide Semiconductor (CMOS) technology. Gate Diffusion Input (GDI) logic is one of the prompting alternatives to CMOS logic to reduce transistors and low-power design. In this work, a novel energy and area efficient 1-bit GDI-based full swing Energy and Area efficient Full Adder (EAFA) with minimum error distance is proposed. The proposed architecture was constructed to mitigate the cascaded effect problem in GDI-based circuits. It is proved by extending the proposed 1-bit GDI-based adder for different 16-bit Energy and Area Efficient High-Speed Error-Tolerant Adders (EAHSETA) segmented as accurate and inaccurate adder circuits. The proposed adder’s design metrics in terms of delay, area, and power dissipation are verified through simulation using the Cadence tool. The proposed logic is deployed to accelerate the convolution process in the Low-Weight Digit Detector neural network for real-time handwritten digit classification application as a case study in the Intel Cyclone IV Field Programmable Gate Array (FPGA). The results confirm that our proposed EAHSETA occupies fewer logic elements and improves operation speed with the speed-up factor of 1.29 than other similar techniques while producing 95% of classification accuracy.

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“…This is due to the need and difficulty, which arises when controlling the mantissa and exponents of IEEE 754 floating points during the calculations. 84…”

Section: Implementations Based On Fixed and Floating Pointmentioning

confidence: 99%

Hardware implementations of computer-generated holography: a review

et al. 2020

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Computer-generated holography (CGH) is a technique to generate holographic interference patterns. One of the major issues related to computer hologram generation is the massive computational power required. Hardware accelerators are used to accelerate this process. Previous publications targeting hardware platforms lack performance comparisons between different architectures and do not provide enough information for the evaluation of the suitability of recent hardware platforms for CGH algorithms. We aim to address these limitations and present a comprehensive review of CGH-related hardware implementations.

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Fixed-Point Convolutional Neural Network for Real-Time Video Processing in FPGA

Cited by 18 publications

References 7 publications

LOCOFloat: A Low-Cost Floating-Point Format for FPGAs.: Application to HIL Simulators

LOCOFloat: A Low-Cost Floating-Point Format for FPGAs.: Application to HIL Simulators

Power and Area Efficient Cascaded Effectless GDI Approximate Adder for Accelerating Multimedia Applications Using Deep Learning Model

Hardware implementations of computer-generated holography: a review

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