Flash Memory Device with `I' Shape Floating Gate for Sub-70 nm NAND Flash Memory

Jung, Sang-Goo; Lee, Jong-Ho

doi:10.1143/jjap.45.l1200

Cited by 9 publications

(3 citation statements)

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“…However, several problems have been arising as a result of the progress of down-scaling of the FG structure to the nanoscale region. In particular, the interference between FGs due to Coulomb interaction is emerging as one of the largest obstacles for FG memories [3][4][5]. Stored charges in neighboring FGs interfere with one another, resulting in undesirable threshold voltage shifts in memory operations.…”

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confidence: 99%

Numerical approach for retention characteristics of double floating-gate memories

Tanamoto

Muraoka

2010

Applied Physics Letters

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We report on a numerical investigation in which memory characteristics of double floating-gate (DFG) structure were compared to those of the conventional single floating-gate structure, including an interference effect between two cells. We found that the advantage of the DFG structure is its longer retention time and the disadvantage is its smaller threshold voltage shift. We also provide an analytical form of charging energy including the interference effect. PACS numbers:Floating-gate (FG) memories are widely used in computers because of their low cost and high density [1,2]. FG memories have progressed rapidly through downscaling using state of the art technology. However, several problems have been arising as a result of the progress of down-scaling of the FG structure to the nanoscale region. In particular, the interference between FGs due to Coulomb interaction is emerging as one of the largest obstacles for FG memories [3][4][5]. Stored charges in neighboring FGs interfere with one another, resulting in undesirable threshold voltage shifts in memory operations. In order to reduce this interference, complicated programming sequences are carried out in the current commercial FG arrays.In the case of locally charged materials such as dielectric materials, it is evident that the electric dipoles exist stably within mutual strong Coulomb interaction. This leads us to consider whether we can construct an "artificial dipole" using a FG system. One of the candidates might be a stacked double floating-gate (DFG) structure [6], in which an additional FG exists between the FG and the control gate in the conventional FG array as shown in Fig. 1(a). Moreover, if the FG becomes as small as a quantum dot [7,8], DFG can be used as a qubit [9], which is a basic element of a quantum computer [10]. Therefore, it is important to clarify the fundamental properties of the DFG structure. The purpose of this paper is to numerically compare the retention time of the DFG structure with that of the conventional single FG (SFG) structure in Si/SiO 2 system, including an interference effect between two cells. We clarify the unique transient behavior of DFG owing to the existence of the additional FG. In order to compare DFG with SFG impartially, we adopt the same equivalent oxide thickness (EOT) for both structures. We also compare read disturbs of both FG structures. Finally, we derive an analytical form of charging energy of DFG and SFG as a function of gate voltages and electron charges.Formulation.-We calculate transient behaviors of a cell where length L and width W of each FG and a distance between neighboring cells X D are set equal as L = W = X D = 23 nm and the height of all FGs is Z = 50 nm for two cases of oxide thickness ( Fig. 1(b)).(We obtain similar results for the L = W =11nm case.) We take dielectric constants and effective mass of Si and oxide SiO 2 as ǫ Si = 11.7, ǫ ox = 3.9, and m Si = 0.19, m ox = 0.5, respectively. The barrier height of SiO 2 is Φ b = 2.9eV. The capacitances are defined bywhere T ox1 , T ox2 a...

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confidence: 99%

Numerical approach for retention characteristics of double floating-gate memories

Tanamoto

Muraoka

2010

Applied Physics Letters

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“…[1][2][3][4] Among the NAND flash memories, tantalum nitride-aluminum oxide-silicon nitride-silicon oxide-silicon (TANOS) flash memory devices have attracted much attention owing to their promising applications in simple-fabrication, high-density, and lowpower flash memory devices. [5][6][7][8] Because the scaling-down process of the conventional TANOS flash memory technology encountered delicate problems of difficult technical challenges and device performance limitations, the use of a multilevel cell (MLC) were suggested to overcome the scaling-down limits of the TANOS flash memories. [9][10][11][12] When the size of the cell is scaled down, it is a critical point to obtain a narrow threshold voltage (V TH ) distribution in the MLC NAND flash memory.…”

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confidence: 99%

Dependence of Electrical Characteristics on the Depth of the Recess Region in the Scaled Tantalum Nitride–Aluminum Oxide–Silicon Nitride–Silicon Oxide–Silicon Flash Memory Devices

Jang

Jin

Kim

et al. 2011

Jpn. J. Appl. Phys.

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Nanoscale tantalum nitride–aluminum oxide–silicon nitride–silicon oxide–silicon (TANOS) memory devices utilizing a recess region were investigated to improve device performance and reduce cell-to-cell interference. The dependence of electrical properties on the depth of the recess region in the TANOS flash memory devices was simulated by using Synopsys TCAD Sentaurus. The cell-to-cell interference characteristics of the TANOS flash memory devices dependent on the recess region were investigated. The drain current at an on-state in the TANOS flash memory devices increased with increasing depth of the recess region owing to the existence of the fringe field generated from the recess region. The coupling ratio of the TANOS flash memory increased with increasing depth of the recess region. The simulation results showed that the cell-to-cell interference in the TANOS flash memory devices decreased with increasing depth of the recess region.

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“…Because mobile devices, such as MP3 players, camcoders, and cellular phones, use NAND flash memory devices as their main data storage device, low-cost and high-density NAND flash memory devices have been particularly attractive because of interest in their promising applications in portable electronic and optoelectronic devices. [1][2][3][4][5][6] Downscaled NAND flash devices have been extensively achieved, more than other types of memory devices, to satisfy the demands of the market. [7][8][9] However, NAND flash memory devices with a 50nm node and beyond have encountered several scale-down problems, such as interference effects between the cells and the short-channel effects.…”

Section: Introductionmentioning

confidence: 99%

Decrease in Interference Effects between Cells for Metal–Oxide–Nitride–Oxide–Silicon NAND Flash Memory Devices with Metal Spacer Layers

Kim¹,

You²,

Kim³

2011

Jpn. J. Appl. Phys.

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Nanoscale metal–oxide–nitride–oxide–silicon (MONOS) NAND flash memory devices with a metal spacer layer were designed to increase the fringing field and the coupling ratio of the control gate and to decrease the interference effects between the cells. The simulation results showed that the drain current and the threshold voltage shift of the MONOS NAND flash memory devices utilizing a metal spacer increased owing to the increase in the fringing field and the coupling ratio. The electric field on the channel surface of the memory devices with a metal spacer layer increased, indicative of the achievement of the maximum fringing field effect, resulting in an increase in the drain current. The simulation results showed that the interference effects for the memory devices utilizing a metal spacer decreased resulting from the shielding of the electric field between neighboring cells.

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Flash Memory Device with `I' Shape Floating Gate for Sub-70 nm NAND Flash Memory

Cited by 9 publications

References 4 publications

Numerical approach for retention characteristics of double floating-gate memories

Numerical approach for retention characteristics of double floating-gate memories

Dependence of Electrical Characteristics on the Depth of the Recess Region in the Scaled Tantalum Nitride–Aluminum Oxide–Silicon Nitride–Silicon Oxide–Silicon Flash Memory Devices

Decrease in Interference Effects between Cells for Metal–Oxide–Nitride–Oxide–Silicon NAND Flash Memory Devices with Metal Spacer Layers

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