Flash memory file caching for mobile computers

Marsh, Brian D.; Douglis, Fred; Krishnan, P.

doi:10.1109/hicss.1994.323153

Cited by 64 publications

(35 citation statements)

References 6 publications

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“…Of interest to a potential space application are techniques that use NAND flash to implement low-power file caches for mobile devices [37,35]. A key feature is the need to cope with the accumulation of errors over time, a mechanism which is well understood [1,46].…”

Section: Open Nand Flash Interface (Onfi)mentioning

confidence: 99%

POSIX and the Verification Grand Challenge: A Roadmap

Freitas

Woodcock

Butterfield

2008

13th IEEE International Conference on Engineering of Complex Computer Systems (Iceccs 2008)

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Section: Open Nand Flash Interface (Onfi)mentioning

confidence: 99%

POSIX and the Verification Grand Challenge: A Roadmap

Freitas

Woodcock

Butterfield

2008

13th IEEE International Conference on Engineering of Complex Computer Systems (Iceccs 2008)

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“…A representative example is using a hard disk and a NAND flash memory (hereafter, a flash or a NAND flash mean a SLC NAND flash unless described otherwise). Combinations of a hard disk and a flash memory have been widely studied and they can be categorized into two groups: one uses a flash memory as a non-volatile cache [5]- [13] and the other uses a flash Table 1 Characteristics of typical small form-factor hard disks and NAND flash memories [4], [14], [20], [21].…”

Section: Use Of Heterogeneous Storage Devicesmentioning

confidence: 99%

DAC: A Device-Aware Cache Management Algorithm for Heterogeneous Mobile Storage Systems

Kim

2008

IEICE Transactions on Information and Systems

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SUMMARYIn recent years, heterogeneous devices have been employed frequently in mobile storage systems because a combination of such devices can supply a synergistically useful storage solution by taking advantage of each device. One important design constraint in heterogeneous storage systems is to mitigate I/O performance degradation stemming from the difference between access times of different devices. To this end, there has not been much work to devise proper buffer cache management algorithms. This paper presents a novel buffer cache management algorithm which considers both I/O cost per device and workload patterns in mobile computing systems with a heterogeneous storage pair of a hard disk and a NAND flash memory. In order to minimize the total I/O cost under varying workload patterns, the proposed algorithm employs a dynamic cache partitioning technique over different devices and manages each partition according to request patterns and I/O types along with the temporal locality. Trace-based simulations show that the proposed algorithm reduces the total I/O cost and flash write count significantly over the existing buffer cache algorithms on typical mobile traces. key words: heterogeneous mobile storage, performance optimization, device-aware cache management, dynamic cache partitioning, workloadaware management

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“…플래시 메모리는 저전력, 강한 충격저 항, 높은 집적도 그리고 대용량 저장매체로써 중요성 및 수용 에 대한 요구를 증대시키고 있다 [2]. 또한 오늘날 하드디스크 를 대치하기 위한 플래시 메모리 연구인 SSD(solid-state disk) 연구가 활발히 진행하고 있다.…”

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The Instruction Flash memory system with the high performance dual buffer system

Jung¹,

Hoon²

2011

Journal of the Korea Society of Computer and Information

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NAND type Flash memory has performing much researches for a hard disk substitution due to its low power consumption, cheap prices and a large storage. Especially, the NAND type flash memory is using general buffer systems of a cache memory for improving overall system performance, but this has shown a tendency to emphasize in terms of data. So, our research is to design a high performance instruction NAND type flash memory structure by using a buffer system. The proposed buffer system in a NAND flash memory consists of two parts, i.e., a fully associative temporal buffer for branch instruction and a fully associative spatial buffer for spatial locality. The spatial buffer with a large fetching size turns out to be effective serial instructions, and the temporal buffer with a small fetching size can achieve effective branch instructions. According to the simulation results, we can reduce average miss ratios by around 77% and the average memory access time can achieve a similar performance compared with the 2-way , victim and fully associative buffer with two or four sizes.▸Keyword : NAND flash memory, cache memory, temporal-spatial locality, Instruction

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Flash memory file caching for mobile computers

Cited by 64 publications

References 6 publications

POSIX and the Verification Grand Challenge: A Roadmap

POSIX and the Verification Grand Challenge: A Roadmap

DAC: A Device-Aware Cache Management Algorithm for Heterogeneous Mobile Storage Systems

The Instruction Flash memory system with the high performance dual buffer system

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