FlashTrie: Beyond 100-Gb/s IP Route Lookup Using Hash-Based Prefix-Compressed Trie

Bando, Masanori; Lin, Yi-Li; Chao, H. Jonathan

doi:10.1109/tnet.2012.2188643

Cited by 45 publications

(51 citation statements)

References 26 publications

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“…They are roughly divided into two: Tree-based [1], [8], [9], [16] and Hash-based [5], [13], [17], [23]. Also, the hash-based compress tree [2] has been proposed. To archive a high-speed lookup, a pipelined binary-search tree (BST) has been proposed [10].…”

Section: Demands For Lookup Architecture In Ipv6 Eramentioning

confidence: 99%

A Memory-Based IPv6 Lookup Architecture Using Parallel Index Generation Units

Nakahara

Sasao

Matsuura

et al. 2015

IEICE Trans. Inf. & Syst.

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Hiroki NAKAHARA †a) , Tsutomu SASAO † †b) , Munehiro MATSUURA † † †c) , Hisashi IWAMOTO † † † †d) , Members, and Yasuhiro TERAO † † † †e) , Nonmember SUMMARYIn the era of IPv6, since the number of IPv6 addresses rapidly increases and the required speed is more than Giga lookups per second (GLPS), an area-efficient and high-speed IP lookup architecture is desired. This paper shows a parallel index generation unit (IGU) for memorybased IPv6 lookup architecture. To reduce the size of memory in the IGU, we use a linear transformation and a row-shift decomposition. A singlememory realization requires O(2 l log k) memory size, where l denotes the length of prefix, while the realization using IGU requires O(kl) memory size, where k denotes the number of prefixes. In IPv6 prefix lookup, since l is at most 64 and k is about 340 K, the IGU drastically reduces the memory size. Also, to reduce the cost, we realize the parallel IGU by using both onchip and off-chip memories. We show a design algorithm for the parallel IGU to store given off-chip and on-chip memories. The parallel IGU has a simple architecture and performs lookup by using complete pipelines those insert the pipeline registers in all the paths. We loaded more than 340 K IPv6 pseudo prefixes on the Xilinx Virtex 6 FPGA with off-chip DDRII+ Static RAMs (SRAMs). Its lookup speed is 1.100 giga lookups per second (GLPS) which is sufficient for the required speed for a next generation 400 Gbps link throughput. As for the normalized area and lookup speed, our implementation outperforms existing FPGA implementations.

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Section: Demands For Lookup Architecture In Ipv6 Eramentioning

confidence: 99%

A Memory-Based IPv6 Lookup Architecture Using Parallel Index Generation Units

Nakahara

Sasao

Matsuura

et al. 2015

IEICE Trans. Inf. & Syst.

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“…Bloom Filters [9] use hash functions extracted from the set of rules, which allow a for a very efficient O(1) lookup, but with false positives. Binary Tries [1], [10] create binary search trees from a set of rules using different types of memories. Memories such as TCAMs have been used in several approaches, but these memories are costly [11].…”

Section: B Fpga-based Solutionsmentioning

confidence: 99%

“…Each time the DDR memory is accessed for a non-preloaded data, the whole page that contains the data is loaded, which is a slow process. If the search address order is known, delay is acceptable [10], but unfortunately the incoming order of destination IP addresses is not predictable. Finally, QDR-II and RLDRAM memories provide a pipelined access.…”

Section: Rule Storage and Lookupmentioning

confidence: 99%

A FPGA-based scalable architecture for URL legal filtering in 100GbE networks

Garnica

López-Buedo

López

et al. 2012

2012 International Conference on Reconfigurable Computing and FPGAs

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Abstract-Legal filtering is common practice in many countries to avoid access to websites with criminal or violent content. This kind of filtering is typically implemented at the edge routers of ISP's core networks, so it is mandatory to support very high bit rates. This paper proposes a hardware-software solution based on FPGAs, which scales up to 100 Gbps Ethernet. A FPGAbased PCIe board equipped with two network interfaces is used to intercept ISP traffic. The FPGA performs an initial filtering of the packets whose destination is potentially forbidden, based on a hash of the destination IP address. Filtered packets are sent to the software application, which inspects them and decides if the URL is actually forbidden or not. This two-level filtering allows for the scalability of the proposed solution to very high bit rates, not only because it simplifies FPGA design, but also because it significantly reduces software load, since potentially forbidden destinations are few. Additionally, this solution adds a minimal latency to most of the packets, and also allows for updating filtering rules without interrupting ISP traffic. The paper presents a proof-of-concept 10GbE implementation of the proposed architecture, as well as an analysis of its scalability up to 100GbE.

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“…While other hardware platforms exist, Field Programmable Gate Arrays (FPGAs) have become the natural choice for high speed networking applications due to various reasons such as abundant resources (memory, logic, etc.,), reconfigurability, high-performance, etc., [13], [20], [6], [3], [11], [2]. Var ious algorithmic solutions can be mapped onto FPGA, and pipelining is often employed to achieve high-performance.…”

Section: Gordon Brebnermentioning

confidence: 99%