FlexBex: A RISC-V with a Reconfigurable Instruction Extension

FPGA-extended Modified Harvard Architecture

“…One of its applications is for the implementation of embedded FPGAs (eFPGAs), also for the purposes of extending hardened cores. A RISC-V SoC with eFPGAs is presented as a use case, which is extended as a separate study with FlexBex [11]. The custom instruction usage is limited to specialised kernels, and concepts like context-switching are not studied.…”

Extending the RISC-V ISA for exploring advanced reconfigurable SIMD instructions

“…Blocking instructions are also supported with minor modification. CAS cas0(clk, net[0], net [1], net [4], net [5]); 29 CAS cas1(clk, net[2], net [3], net [6], net [7]); 30 31 CAS cas2(clk, net [4], net [7], net [8], net [11]); 32 CAS cas3(clk, net [5], net [6], net [9], net [10]); 33 34 CAS cas4(clk, net [8], net [9], net [12], net [13]); 35 CAS cas5(clk, net [10], net [11], net [14], net [15]); 36 37 // Assigning input and output to wires in the sorting network 38 // (only using 1 input and 1 output reg. for this instruction) 39 for (i=0; i<4; i=i+i) assign net[i]=in_vdata1[32*(i+1)-1-:32]; 40 assign out_vdata1={net [12], net [13], net [14], net [15]}; The example instruction implementation in Algorithm 1 is a bitonic sorter of 4 inputs.…”

“…With respect to the softcore implementation, the closest research are from Dao et al who presented FlexBex [9], an open-source framework for embedding small FPGAs in a modified Ibex RISC-V core [45]. Although it provides a form of SIMD functionality, it is for embedded solutions and without a cache, and the operation is done on multiple 32-bit registers.…”

“…Modern general purpose processors (CPUs) support a wide range of single-instruction-multiple data (SIMD) instructions [15] as a way to accelerate applications that exhibit data-level parallelism. While there can be notable performance gains in certain applications [5], the instruction set extensions become bloated with overspecialised instructions [9], and sometimes it is difficult to express efficiently a parallel task using a fixed set of SIMD extensions [8].…”

“…In combination with the openness of the RISC-V instruction set, and its support for custom instructions [43], this is a great time to start considering custom SIMD instructions on general purpose CPUs. Small FPGAs can be integrated, to implement custom instructions [9] and are demonstrated to improve the performance over existing extensions significantly [30,31]. In the literature, the exploration of custom instructions on CPUs, and specifically SIMD, is rather limited, even though small reconfigurable regions working as instructions is a promising idea and possibly the future of acceleration.…”