Flexible design and implementation of QC-Based LDPC decoder architecture for on-line user-defined matrix downloading and efficient decoding

Shih, Xin-Yu; Chou, Hong-Ru

doi:10.1016/j.vlsi.2018.07.008

Cited by 6 publications

(4 citation statements)

References 27 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For the communication systems and the standards, it is known that an optimized irregular LDPC code has better performance than a regular LDPC code [19], besides, the quasi cyclic LDPC (QC-LDPC) codes showed good performances for large codeword length [20]- [22]. The decoding complexity is proportional to / , where is the number of links between the check nodes and the variable nodes, and =k/n is the code rate [23].…”

Section: Research Methods 21 Decoding Algorithmsmentioning

confidence: 99%

An improvement and a fast DSP implementation of the bit flipping algorithms for low density parity check decoder

Razi

Benhayoun

Mansouri

et al. 2021

IJECE

View full text Add to dashboard Cite

<span lang="EN-US">For low density parity check (LDPC) decoding, hard-decision algorithms are sometimes more suitable than the soft-decision ones. Particularly in the high throughput and high speed applications. However, there exists a considerable gap in performances between these two classes of algorithms in favor of soft-decision algorithms. In order to reduce this gap, in this work we introduce two new improved versions of the hard-decision algorithms, the adaptative gradient descent bit-flipping (AGDBF) and adaptative reliability ratio weighted GDBF (ARRWGDBF). An adaptative weighting and correction factor is introduced in each case to improve the performances of the two algorithms allowing an important gain of bit error rate. As a second contribution of this work a real time implementation of the proposed solutions on a digital signal processors (DSP) is performed in order to optimize and improve the performance of these new approchs. The results of numerical simulations and DSP implementation reveal a faster convergence with a low processing time and a reduction in consumed memory resources when compared to soft-decision algorithms. For the irregular LDPC code, our approachs achieves gains of 0.25 and 0.15 dB respectively for the AGDBF and ARRWGDBF algorithms.</span>

show abstract

Section: Research Methods 21 Decoding Algorithmsmentioning

confidence: 99%

An improvement and a fast DSP implementation of the bit flipping algorithms for low density parity check decoder

Razi

Benhayoun

Mansouri

et al. 2021

IJECE

View full text Add to dashboard Cite

show abstract

“…This method generates robustly a synchronous clock for data recovery. A quasi cycle LDPC decoder is implemented using a 40‐nm CMOS process in Shih and Chou . Its performance is analyzed in terms of power consumption, clock frequency etc and used for 802.11 applications.…”

Section: Overview Of Conventional Techniques For Viterbi Decodermentioning

confidence: 99%

“…A quasi cycle LDPC decoder is implemented using a 40-nm CMOS process in Shih and Chou. 29 Its performance is analyzed in terms of power consumption, clock frequency etc and used for 802.11 applications. A salient object is separated from the clustered background using a deep convolutional neural network.…”

Section: Pipelined Architecturementioning

confidence: 99%

Power efficient low latency architecture for decoder: Breaking the ACS bottleneck

Radha

Shylu

Nagabushanam

2019

Circuit Theory & Apps

View full text Add to dashboard Cite

Summary Viterbi decoder (VD) is the majority used decoder for convolutional codes which play a role in WLAN and WSN applications. The trellis in VD needs proper analysis to calculate the metric at each stage to obtain a shortest path from every state to the next state. Existing techniques in VD design are namely (a) pipelined architecture, (b) modular ACS and buffers technique, and (c) quasi cyclic trellis technique. The key challenge of the VD trellis circuit is to attain high throughput and better latency performance with low power consumption without affecting hardware complexity of VD. This paper presents several of conventional methods used in VD. We also proposed a new method for VD with K the constraint length as multiple of M, the radix in trellis to calculate the shortest survival path to travel in trellis. The proposed VD is simulated using Xilinx. Use of a trace back approach in the proposed Viterbi decoder with capacitive and resistive feedback yields better throughput, latency, and power consumption with respect to other techniques. The static power outputs obtained in RE, shift update, and selective update methods using Libero IDE are also compared.

show abstract

“…The existing studies have demonstrated the practical importance of the LDPC‐based decoding algorithms and its application which is oriented towards the design and development of LDPC decoder prototype modules 14 . With recent advancements in the field of Very Large Scale Integration (VLSI) technology at its prime, many researchers have successfully demonstrated the importance of reconfigurable LDPC decoders and its applications 15 . However, the main bottleneck in decoder design arises from the need for feasibility and hardware constraints which leads to longer computation time and complications in design efforts.…”

Section: Introductionmentioning

confidence: 99%

Certain investigations on recent advances in the design of decoding algorithms using low‐density parity‐check codes and its applications

Roberts¹,

Kumari

Anguraj³

2021

Int J Communication

View full text Add to dashboard Cite

Summary Information theory coding is an impressive and most celebrated field of research that has spawned numerous extremely important solutions to the intractable problems of secure data communications. Recent advancements in error control coding methods have seen a huge surge in using low‐density parity‐check (LDPC) code‐based decoding algorithms to solve imperative issues related to reliable data transmission and reception. Till date, extensive research efforts have been consistently being made on LDPC codes which focus on algorithm‐driven and hardware‐realization‐based approaches. The main intension of this research work is to provide an extensive systematic elucidation on the recent advancements in LDPC decoding algorithms. In addition, a thorough performance evaluation and analysis of several outstanding LDPC decoding techniques is presented. Finally, conclusions are drawn by summarizing the important research findings, interesting open problems, current challenges and broader perspectives for future directions of research.

show abstract

Flexible design and implementation of QC-Based LDPC decoder architecture for on-line user-defined matrix downloading and efficient decoding

Cited by 6 publications

References 27 publications

An improvement and a fast DSP implementation of the bit flipping algorithms for low density parity check decoder

An improvement and a fast DSP implementation of the bit flipping algorithms for low density parity check decoder

Power efficient low latency architecture for decoder: Breaking the ACS bottleneck

Certain investigations on recent advances in the design of decoding algorithms using low‐density parity‐check codes and its applications

Contact Info

Product

Resources

About