Flexible Routing Architecture Generation for Domain-Specific Reconfigurable Subsystems

2008

IEEE Trans. VLSI Syst.

Reconfigurable hardware is ideal for use in systems-on-a-chip (SoC), as it provides both hardware-level performance and post-fabrication flexibility. However, any one architecture is rarely equally optimized for all applications. SoCs targeting a specific set of applications can greatly benefit from incorporating customized reconfigurable logic instead of generic field-programmable gate-array (FPGA) logic. Unfortunately, manually designing a domain-specific architecture for every SoC would require significant design time. Instead, this paper discusses our initial efforts towards creating a reconfigurable hardware generator capable of automatically creating flexible, yet domain-specific, designs. Our tests indicate that our generated architectures are more than 5 smaller than equivalent FPGA implementations and nearly as area-efficient as standard cell designs. We also use a novel technique employing synthetic circuit generation to demonstrate the flexibility of our architecture generation techniques.

Section: Introductionmentioning

confidence: 86%

Automatic Design of Reconfigurable Domain-Specific Flexible Cores

Compton

2008

IEEE Trans. VLSI Syst.

“…However, this would defeat the purpose of the minimalist cASIC. Techniques from the Totem Project to generate more flexible domain-specific reconfigurable hardware have been published elsewhere [17].…”

Section: Logic Generationmentioning

confidence: 99%

“…However, at this point we are no longer performing the task targeted by this article. The design would then approach a domain-flexible architecture in style, and we suggest that other architecture generation techniques designed for flexible domain-specific architectures would be more appropriate [17].…”

Section: Future Directionsmentioning

confidence: 99%

Automatic Design of Area-Efficient Configurable ASIC Cores

Compton

2007

IEEE Trans. Comput.

Self Cite

Reconfigurable hardware has been shown to provide an efficient compromise between the flexibility of software and the performance of hardware. However, even coarse-grained reconfigurable architectures target the general case, and miss optimization opportunities present if characteristics of the desired application set are known. Efficiency can be increased by restricting the structure to support a class or a specific set of algorithms, while still providing flexibility within that set. By generating a custom array for a given computation domain, we explore the design space between an ASIC and an FPGA. However, the manual creation of these customized reprogrammable architectures would be a labor-intensive process, leading to high design costs. Instead, we propose automatic reconfigurable architecture generation specialized to given application sets. This article discusses configurable ASIC (cASIC) architecture generation that creates hardware on average up to 12.3x smaller than an FPGA solution with embedded multipliers and 2.2x smaller than a standard cell implementation of individual circuits.

“…Previous work in Totem has focused on using a 1-D RaPiD array [1][2][3][4] in order to provide reconfigurable architectures for domains that use ALUs, Multipliers, RAMs, and other coarse grained units. But many domains do not benefit from the use of coarse-grained units, and would require a finer-grained fabric.…”

Section: Introductionmentioning

confidence: 99%

Automatic Creation of Reconfigurable PALs/PLAs for SoC

Holland

Field Programmable Logic and Application

2004

Self Cite

Abstract. Many System-on-a-Chip devices would benefit from the inclusion of reprogrammable logic on the silicon die, as it can add general computing ability, provide run -time reconfigurability, or even be used for post -fabrication modifications. Also, by catering the logic to the SoC domain, additional area/delay/power gains can be achieved over current, more general reconfigurable fabrics. This paper presents tools that automate the creation of domain specific PLAs and PALs for SoC, including an Architecture Generator for making optimized arrays and a Layout Generator for creating efficient layouts. By intelligently mapping netlists to PLA and PAL arrays, we can reduce 60%-70% of the programmable connections in the array, creating delay gains of 15%-30% over unoptimized arrays.