FlexiCheck: An Adaptive Checkpointing Architecture for Energy Harvesting Devices

Singla, Priyanka; Singh, Shubhankar Suman; Sarangi, Smruti R.

doi:10.23919/date.2019.8715130

Cited by 7 publications

(3 citation statements)

References 18 publications

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“…As RAM access is known to be a major contributor to dynamic power consumption in FPGAs, especially at high clock rates, the increase in dynamic power in large high-throughput sketches might be significant. To our knowledge, the sketch in [28] is the only hardware sketch to be optimized for low power consumption. This sketch is aimed at small energy-harvesting devices and works simply by deploying a filtering stage that blocks portions of the stream to reduce RAM accesses at the expense of reduced accuracy.…”

Section: Related Work: Fpga-based Data Stream Frequency Estimatorsmentioning

confidence: 99%

“…For moderately skewed inputs (α = 1), m had to be large to achieve reasonable reduction in memory access rate. For heavily skewed inputs, the reduction in memory access was significant, even for small values of m. Since, RAM is the dominant resource in a sketch, the optimization could be used to achieve significant reduction in total dynamic power consumption without loss in accuracy as in the stream filtering power optimization technique in [28]. ter (α) values ranging from 1 to 1.5, without considering hash collisions.…”

Section: Reduced Memory Accesses In Skewed Streamsmentioning

confidence: 99%

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High-Level Design Optimizations for Implementing Data Stream Sketch Frequency Estimators on FPGAs

Ebrahim

2022

Electronics

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This paper presents simple yet effective optimizations for implementing data stream frequency estimation sketch kernels using High-Level Synthesis (HLS). The paper addresses design issues common to sketches utilizing large portions of the embedded RAM resources in a Field Programmable Gate Array (FPGA). First, a solution based on Load-Store Queue (LSQ) architecture is proposed for resolving the memory dependencies associated with the hash tables in a frequency estimation sketch. Second, performance fine-tuning through high-level pragmas is explored to achieve the best possible throughput. Finally, a technique based on pre-processing the data stream in a small cache memory prior to updating the sketch is evaluated to reduce the dynamic power consumption. Using an Intel HLS compiler, a proposed optimized hardware version of the popular Count-Min sketch utilizing 80% of the embedded RAM in an Intel Arria 10 FPGA, achieved more than 3x the throughput of an unoptimized baseline implementation. Furthermore, the sketch update rate is significantly reduced when the input stream is skewed. This, in turn, minimizes the effect of high throughput on dynamic power consumption. Compared to FPGA sketches in the published literature, the presented sketch is the most well-rounded sketch in terms of features and versatility. In terms of throughput, the presented sketch is on a par with the fastest sketches fine-tuned at the Register Transfer Level (RTL).

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Section: Related Work: Fpga-based Data Stream Frequency Estimatorsmentioning

confidence: 99%

Section: Reduced Memory Accesses In Skewed Streamsmentioning

confidence: 99%

High-Level Design Optimizations for Implementing Data Stream Sketch Frequency Estimators on FPGAs

Ebrahim

2022

Electronics

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“…Task-based programming models such as Mayfly [15], Chain [16], Flexicheck [17] and Alpaca [18] overcome intermittency by ensuring atomic computing tasks are completed each power cycle. There is a large burden on the programmer to break the code into tasks and complex code structures.…”

Section: Background and Related Workmentioning

confidence: 99%

Improving the Forward Progress of Transient Systems

Daulby

Savanth

Merrett

et al. 2021

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Emerging applications for Internet of Things devices demand smaller mass, size and cost whilst increasing capability and reliability. Energy harvesting can provide power to these ultra-constrained devices, but introduces unreliability, unpredictability and intermittency. Schemes for wireless sensors without batteries or supercapacitors overcome intermittency through saving system state into non-volatile memory before the supply drops below the minimum operating voltage, termed transient or intermittent computing. However, this introduces significant time and energy overheads. This paper presents two schemes that significantly reduce these overheads: entering a sleep mode to avoid saving state and utilising direct memory access (DMA) when state saves are required. Time and energy previously wasted on state saves can instead be used to perform useful computation, termed "forward progress". We practically validate the proposed approaches across a range of energy sources and IoT benchmarks and demonstrate up to 46.8% and 40.3% increase in forward progress and up to 91.1% and 85.6% reduction in overheads for each scheme respectively.

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