Flip-chip Packages with Periphery Cu Pillar Bumps as Wire Bond Replacement—Design, Modeling &amp; Characterization

Li, Zhe; Tan, Siow Chek; Yew, Yee Huan; Teh, Pheak Ti; Lee, MJ; Xie, John

doi:10.4071/isom-2013-tp21

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(1 citation statement)

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“…The critical steps are bumping and chip-onchip assembly by Thermal Compression bonding with NonConductive Paste (TCNCP). TCNCP yield is sensitive to CoC alignment which depends on the planarity and topology of copper pillar micro-bumps [4]. Face-to-Face stacking is at early phase of technology development.…”

Section: Introductionmentioning

confidence: 99%

Design and package technology development of Face-to-Face die stacking as a low cost alternative for 3D IC integration

Xie

2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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F2F stacking provides an alternative 3D packaging solution for multi-chip integration without use of TSV. High density interconnection can be achieved with direct Face-toFace (F2F) stacking to enable high bandwidth die to die interface. Simplified stacking process and lower development cost make F2F stacking an attractive solution for cost sensitive applications. A comparative study of performance was performed on F2F stacked Field Programmable Gate Array (FPGA) die in a flip chip organic package. The paper first presents thermal analysis to address power density increase, hot spot and temperature variations in the F2F package. Next the paper focuses on electrical performance validation including both IO and power delivery analysis. With appropriate chip design and optimization, we demonstrate that F2F stacking induced thermal and electrical impacts can be controlled to meet speed and performance specs equivalent to 2D system. The manufacturing design rules have been optimized to meet yield requirements as well as ensuring product reliability. IntroductionIn recent years, 3D IC integration has attracted a great interest in semiconductor industry as a "More Than Moor" approach to break the silicon scaling trend [1]. Increasingly, traditional silicon process scaling alone can no long meet system performance, throughput and power requirements. 3D stacking enables more functional integration than single chip solution. Using through silicon via (TSV) to build 3D stacks of chips makes it possible to eliminate long run of interconnect lines in a 2D system. Power consumption is also reduced because of short interconnect path between active devices and lower IO drive strength to drive the short interconnects [2]. 2.5D and 3D packaging are being actively investigated. In order to achieve manufacturability readiness and cost effectiveness, the entire 3D fabrication sequence requires seamless integration from foundry to OSAT back-end process.Though TSV technologies and 3D integration hold much promise, the industry also realized that the new technology will take time to get established in supply chain and drive volume production. While TSV and 3D technology development continues to improve, a whole variety of interim interconnect/packing solutions are being developed to address the bandwidth and scaling density demands. Direct Face-toFace stacking through high density micro joints provides an alternative 3D packaging solution for multi-chip integration with low cost [3]. F2F stacking offers silicon grade interconnect density IO driver and reduced wiring parasitics for a high performance chip-to-chip interface. F2F packaging also has a time-to-market advantages compared to 3D IC

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Section: Introductionmentioning

confidence: 99%