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In order to achieve substrate routing densities required for high pin count flip chip package, Electroless Nickel immersion Gold (ENIG) substrates have been the technology of choice. However, ENIG substrates are found to be more susceptible to brittle fracture at the Nickel to intermetallic interface during high strain rate events. This mode has been sporadically found in PCB assembly and handling operations involving excessive and uncontrolled flexural loads on the PC boards. The unpredictable nature of this failure mode has driven suppliers to look for alternatives to ENIG. In this paper, Electrolytic Nickel-Gold and Solder on Pad (SOP) are studied and contrasted against ENIG. A significant outcome of this work is the identification of a viable surface finish with improved toughness to withstand mechanical shocks in early assembly and with continued good long term reliability. IntroductionNickel based surface finish is a popular choice for high density Flip chip BGA substrates because the processes generates a flat and solderable surface. The use of Electroless Nickel Immersion Gold (ENIG) surface finish has steadily increased in preference to Electrolytic-NiAu over the years because the Electroless process allows for increased routing densities by eliminating the need for plating buss bars. In addition to planarity, Nickel based finishes offer several other advantages such as higher substrate shelf-life, improved corrosion resistance, a larger assembly process window, better thermal resistance over several temperature excursions, and good reworkability. With these advantages, the ENIG surface finish has become the most popular option for flip chip BGA's, and over the years it has demonstrated the capability to consistently meet industry standard quality and reliability requirements However, during the early stages of the ENIG development processes, the plating technology was plagued with "black pad" failure mode. This failure mechanism is the result of corrosion that can occur during the auto-catalytic immersion gold process, and has been studied in detail [1-3]. The gold deposition selectively attacks grain boundaries in the phosphorus enriched nickel layer, causing pitting corrosion and mud-flat cracks in the Electroless nickel layer. The existence of black pad can be detected if the failure mode in conventional ball-shear testing is separation at the ENIG interface, instead of failure in the bulk solder [4]. The process variables required to eliminate black pad have subsequently been studied and optimized [4,5].With increasing volumes of flip chips, there have been sporadic reports of another type of brittle solder joint failure in PCB assembly and handling operations [6] caused by excessive and uncontrolled PCB flexural loads. Similar to black-pad, the brittle fractures in assembly operations also

F2F stacking provides an alternative 3D packaging solution for multi-chip integration without use of TSV. High density interconnection can be achieved with direct Face-toFace (F2F) stacking to enable high bandwidth die to die interface. Simplified stacking process and lower development cost make F2F stacking an attractive solution for cost sensitive applications. A comparative study of performance was performed on F2F stacked Field Programmable Gate Array (FPGA) die in a flip chip organic package. The paper first presents thermal analysis to address power density increase, hot spot and temperature variations in the F2F package. Next the paper focuses on electrical performance validation including both IO and power delivery analysis. With appropriate chip design and optimization, we demonstrate that F2F stacking induced thermal and electrical impacts can be controlled to meet speed and performance specs equivalent to 2D system. The manufacturing design rules have been optimized to meet yield requirements as well as ensuring product reliability. IntroductionIn recent years, 3D IC integration has attracted a great interest in semiconductor industry as a "More Than Moor" approach to break the silicon scaling trend [1]. Increasingly, traditional silicon process scaling alone can no long meet system performance, throughput and power requirements. 3D stacking enables more functional integration than single chip solution. Using through silicon via (TSV) to build 3D stacks of chips makes it possible to eliminate long run of interconnect lines in a 2D system. Power consumption is also reduced because of short interconnect path between active devices and lower IO drive strength to drive the short interconnects [2]. 2.5D and 3D packaging are being actively investigated. In order to achieve manufacturability readiness and cost effectiveness, the entire 3D fabrication sequence requires seamless integration from foundry to OSAT back-end process.Though TSV technologies and 3D integration hold much promise, the industry also realized that the new technology will take time to get established in supply chain and drive volume production. While TSV and 3D technology development continues to improve, a whole variety of interim interconnect/packing solutions are being developed to address the bandwidth and scaling density demands. Direct Face-toFace stacking through high density micro joints provides an alternative 3D packaging solution for multi-chip integration with low cost [3]. F2F stacking offers silicon grade interconnect density IO driver and reduced wiring parasitics for a high performance chip-to-chip interface. F2F packaging also has a time-to-market advantages compared to 3D IC

Cu pillar is an emerging interconnect technology which offers many advantages compared to traditional packaging technologies. This paper presents a novel packaging solution with periphery fine pitch Cu pillar bumps for low cost and high performance Field Programmable Gate Array (FPGA) devices. Wire bonding has traditionally been the choice for low cost implementation of memory interfaces and high speed transceivers. Migration to Cu pillar technology is mainly driven by increasing demand for IO density and package small form factor. Cu pillar bumps also offer significant improvement on electrical performance compared to wire bonds. This paper presents Cu pillar implementation in an 11×11mm flip chip CSP package. Package design is optimized for serial data transport up to 6.114Gbps to meet CPRI_LVII and PCIe Gen2 compliance requirements. Package design strategy includes die and package co-design, SI/PI modeling and physical layout optimization.

3D IC is the viable revolutionary technology that will enable system-level integration, miniaturization, optimal power management, increased data bandwidth, and eventually reduced system cost. Like any breakthrough technologies, it faces many challenges. Design methodology, integration technology, manufacturing process and new industrial ecosystem are the areas of focus. This paper will discuss these challenges and Altera's 3D integration development effort. 2.5D is an intermediate path to true 3D IC using silicon interposer and TSV (Through-Si-Via) stacking. The 2.5D stacking configuration offers different form factor, interconnect path, and thermal management options than monolithic packages, which could help to reduce system level power and thermal management pressure. It offers silicon level interconnect density, low inductive path and wide IO application. However, it's power delivery system (PDN) could be the bottleneck for the system to perform at the intended bandwidth and speed. Thus, the whole system, IC-Interposer-Package-PCB, must be considered holistically, and trade off study and compensation mechanism development are needed in such complex system level integration. There are many different 2.5D integration manufacturing flows currently under development. They can be categorized into two major flow options: Attaching interposer to substrate first, which can be called CoCoS (Chip on Chip on Substrate); or attaching device silicon to interposer first, which is also called CoWoS (Chip on Wafer on Substrate). The major challenges are in the areas of manufacturing process window and yield, thin wafer handling, testability and overall cost of the integration process. ,). This paper will discuss design consideration, manufacturability analysis, Logic/memory devices and silicon interposer interaction, and thermal management to enable the 2.5D integration. System level characterization and correlation with simulations are performed. The challenge of new supply-customer model and industrial ecosystem development associated with 2.5D integration will also be discussed.