Flipchip bump integrity with copper/ultra low-k dielectrics for fine pitch flipchip packaging

Yoon, Seung Wook; Kripesh, V.; Yu, Li; Yong, Li Chao; Jeffrey, Su Yong Ji; Iyer, M.K.

doi:10.1109/ectc.2004.1320334

Cited by 8 publications

(1 citation statement)

References 2 publications

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“…Placing low-k material at this high stress location will negatively impact the reliability of the entire low-k stack. The impact of increasing number of metal layers has also been evaluated [3][4]. Thicker metal layer structures are more prone to fracture than thinner metal layer structures.…”

Section: Introductionmentioning

confidence: 99%

Structural Design and Optimization of 65nm Cu/low-k Flipchip Package

Ong

Zhang

Kripesh

et al. 2007

2007 9th Electronics Packaging Technology Conference

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The trend toward finer pitch and higher performance integrated circuits (ICs) devices has driven the semiconductor industry to incorporate copper and low-k dielectric materials. However, the low-k materials have lower modulus and poorer adhesion compared to the common dielectric materials. Thus, thermo-mechanical failure is one of the major bottlenecks for development of a Cu/low-k larger die flip chip package. Very low modulus underfills must also be avoided because low modulus underfills transfer too much stress to the bumps which result in bump cracking in TC testing. A 2D plane strain analysis was performed to investigate the reliability of Chartered's C65nm 2lx2lmm 9metal Cu/ low-k, chips with 150um interconnect pitch in a FCBGA package. A series of parametric studies are performed by using Polymer Encapsulated Dicing Lane Technology (PEDL) to reduce 1 layer of FSG, variation of Cu post height, die thickness, substrate thickness, and underfill selection. The results obtained from the reduction of the stress in the low-k structure and the inelastic energy in the solder bumps modeling is useful to formulate design guidelines for packaging of large dies.

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Section: Introductionmentioning

confidence: 99%

Structural Design and Optimization of 65nm Cu/low-k Flipchip Package

Ong

Zhang

Kripesh

et al. 2007

2007 9th Electronics Packaging Technology Conference

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150 μm Pitch Pb-Free Flipchip Packaging with Cu/Low-k Interconnects

Yoon

Kripesh

Viswanath

et al. 2005

Proceedings Electronic Components and Technology, 2005. ECTC '05.

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150 μm pitch flipchip packaging with Pb-free solder and Cu/low-k interconnects

Yoon

Kripesh

et al.

Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)

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In this paper, low-k test vehicles with four Cu layers are fabricated using Cu dual damascene process. Polymer encapsulation and metal redistribution is applied using wafer integration technology to minimize the stress from the solder bump pad to low-k ILD(in1erlayer dielectric). Two different interconnections were studied; i) Pb-free solder bump and ii) copper column. Ti/NiV/CdAu UBM is deposited on the Cdlow-k wafers and Sn-4.0Ag-0.5Cu Pb-free solder are bumped for solder interconnection. For copper column interconnection, thick PR process is developed and optimized for electro Cu plating'and solder is deposited on the top of Cu post. Bump shear test is carried out to evaluate the bump bonding and analyzed the failure. In order to investigate UBM and solder joint reliability, multiple reflows were carried out. Microstructure observation and failure analysis were performed and observed with optical and electron microscopy. The paper will also present the. reliability and failure analysis studies carried out in characterizing the UBM structures.

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Flipchip bump integrity with copper/ultra low-k dielectrics for fine pitch flipchip packaging

Cited by 8 publications

References 2 publications

Structural Design and Optimization of 65nm Cu/low-k Flipchip Package

Structural Design and Optimization of 65nm Cu/low-k Flipchip Package

150 μm Pitch Pb-Free Flipchip Packaging with Cu/Low-k Interconnects

150 μm pitch flipchip packaging with Pb-free solder and Cu/low-k interconnects

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Flipchip bump integrity with copper/ultra low-k dielectrics for fine pitch flipchip packaging

Cited by 8 publications

References 2 publications

Structural Design and Optimization of 65nm Cu/low-k Flipchip Package

Structural Design and Optimization of 65nm Cu/low-k Flipchip Package

150 &#x003BC;m Pitch Pb-Free Flipchip Packaging with Cu/Low-k Interconnects

150 μm pitch flipchip packaging with Pb-free solder and Cu/low-k interconnects

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150 μm Pitch Pb-Free Flipchip Packaging with Cu/Low-k Interconnects