Floating Body DRAM with Body Raised and Source/Drain Separation

Abstract

One-Transistor (1T) DRAMs are one of the potential replacements for conventional 1T-1C dynamic memory cells for future scaling of embedded and stand-alone memory architectures. In this work, a scaled (channel length 10nm) floating body 1T memory device architecture with ultra-thin body is studied, which uses a combined approach of a body raised storage region and separated source/drain regions having the role to reduce thermal and field enhanced band-to-band recombination. The physical mechanisms along the geometry and bias scaling are discussed in order to address the requirements of embedded or stand-alone applications. Two-dimensional device simulations show that, with proper optimization of the geometry and bias, the combined approach allows the increase of the retention time and of the programming window by more than one order of magnitude.

Disturbance Characteristics of 1T DRAM Arrays Consisting of Feedback Field-Effect Transistors

“…Nevertheless, the conventional 1T–1C DRAM technology has run up against the limitation of scaling down because the footprint of the capacitor affects the retention time [ 4 , 5 , 6 ]. Hence, 1T DRAM with a capacitorless structure has attracted attention in DRAM technology [ 7 , 8 , 9 , 10 , 11 ]. Meanwhile, feedback field-effect transistors (FBFETs) with p + –n–p–n + silicon nanowires meet the qualifications for 1T DRAM owing to their inherent characteristics such as near-zero subthreshold swings (SSs) and bistable characteristics [ 11 , 12 , 13 , 14 , 15 , 16 ].…”