Floating Inductance Simulators Based on Active Components

Zhou, Xifeng; Zeng, Rongzhou

doi:10.12783/dtetr/apetc2017/11401

Cited by 3 publications

(4 citation statements)

References 18 publications

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“…Although the circuits reported in [5,6] are electronically tunable, the large number of capacitors and resistors which their values must trim is their weakness. The circuits reported in [7,8,10,11] are electronically tunable but they can provide only +L. The circuits reported in [9,[12][13][14][15] are not electronically tunable.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…A survey of recent literature reveals that various approaches are used in the realization of floating inductors [5][6][7][8][9][10][11][12][13][14][15]. In [5], a digitally tunable floating inductor using two current differential amplifiers (CDAs), two resistors and an array of five floating capacitors, each one connected to a switch, is reported.…”

Section: Introductionmentioning

confidence: 99%

“…Unfortunately, the achieved inductance lacks electronic tuning capability, and its operation relies on the matching between the used resistors. The topology reported in [10] utilizes one differential voltage current conveyor (DVCC), one current controlled current conveyor (CCCII), one grounded resistor and one floating capacitor. Using the electronic controlling capability of CCCII, the achieved inductor is electronically tunable.…”

Section: Introductionmentioning

confidence: 99%

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Realization of an Electronically Tunable Resistor-Less Floating Inductance Simulator Using VCII

et al. 2022

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In this paper, a new implementation of an electronically tunable resistor-less floating inductance simulator using a second-generation voltage conveyor (VCII) is presented. The proposed circuit is resistor-free (benefiting from the intrinsic resistors at the Y terminals of the employed VCIIs) and composed of three VCIIs and a single grounded capacitor. Using a control current (Icon), the value of impedance at the Y terminal of the VCII is varied, whereby the value of the simulated inductance is tuned. The proposed circuit is designed at a transistor level using 0.18 µm TSMC CMOS parameters and ±0.9 V supply voltage. PSpice simulations are carried out to confirm the effectiveness of the proposed circuit. For a range of Icon from 0 µA to 50 µA, the value of the simulated L can be varied from −576 µH to −324 µH and from +316 µH to +576 µH for negative and positive simulators, respectively, in the frequency range of 100 kHz–3 MHz. Favorably, the value of the series resistance remains below 76 Ω. Simulation results show an error value below 4.8% and power consumption variation is from 1.64 mW to 1.92 mW. Moreover, application of the proposed circuit as a standard band-pass RLC filter is also included.

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Section: Simulation Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Realization of an Electronically Tunable Resistor-Less Floating Inductance Simulator Using VCII

et al. 2022

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“…It used three Current Feedback Operational Amplifiers (CFOA) and three passive components, two of which will control the value of the simulated impedance. The authors in [5] presented two floating inductance simulators. The main drawback of these two designs is the use floating capacitor between terminals X and Y and the maximum inductance in both designs is 1.1mH.…”

Section: Introductionmentioning

confidence: 99%

Realization of a Large Values Floating and Tunable Active Inductor

Al-Absi

2019

IEEE Access

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This paper presents a new design for active inductor (AI) realization in addition to capacitance and resistance multipliers. The design uses one current conveyor (CCII±) and one dual-output transconductance amplifier(DO-OTA) and a grounded capacitor. The functionality of the design is confirmed using experimental verification and simulation. Simulation results show that the realized inductance is tunable be tuned from few mH to 2H and more and the multiplication factor for the resistance multiplier is more than 2200 while the capacitance multiplication factor is around 500. A CMOS version of the AI is designed and simulated using Tanner Tspice in 0.18µm CMOS technology. The simulation results confirm the functionality of the design.INDEX TERMS Tunable active inductance, resistance multiplier, capacitance multiplier, integrated circuits.

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