Floating point Cordic

Hekstra, G.J.; Deprettere, E.F.

doi:10.1109/arith.1993.378100

Cited by 29 publications

(7 citation statements)

References 5 publications

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“…On the other hand, a FP Z coordinate (angle) was used by [4] and [21] for their word-serial implementation. In the latter, all operations are performed in FP format, which requires a large area occupation, considering it is an iterative architecture.…”

Section: Previous Work On Fp Cordic and Fp Givens Rotationmentioning

confidence: 99%

“…In the latter, all operations are performed in FP format, which requires a large area occupation, considering it is an iterative architecture. On the contrary, the design in [4] only uses a full FP representation for the angle, but the computation of iterations is performed using block FP (i.e., exponents remains constant through the iterations). They state that renormalization of significands between consecutive additions are expensive and not required [4].…”

Section: Previous Work On Fp Cordic and Fp Givens Rotationmentioning

confidence: 99%

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Efficient Floating-Point Givens Rotation Unit

Hormigo,

Muñoz

2020

Preprint

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High-throughput QR decomposition is a key operation in many advanced signal processing and communication applications. For some of these applications, using floating-point computation is becoming almost compulsory. However, there are scarce works in hardware implementations of floating-point QR decomposition for embedded systems. In this paper, we propose a very efficient high-throughput floating-point Givens rotation unit for QR decomposition. Moreover, the initial proposed design for conventional number formats is enhanced by using the new Half-Unit Biased format. The provided error analysis shows the effectiveness of our proposals and the trade-off of different implementation parameters. FPGA implementation results are also presented and a thorough comparison between both approaches. These implementation results also reveal outstanding improvements compared to other previous similar designs in terms of area, latency, and throughput.

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Section: Previous Work On Fp Cordic and Fp Givens Rotationmentioning

confidence: 99%

Section: Previous Work On Fp Cordic and Fp Givens Rotationmentioning

confidence: 99%

Efficient Floating-Point Givens Rotation Unit

Hormigo,

Muñoz

2020

Preprint

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“…As with SVD, the QRD algorithm uses a sequence of Givens rotations to transform the incoming data matrix into an upper triangular matrix. The CORDIC algorithm [11], [12] provides an attractive means for implementing the arithmetic units required in typical SVD/QRD processing elements (PEs) as these enable the efficient implementation of plane rotation and phase computation [13]- [17].…”

Section: Cordic Algorithm For Svd and Qrdmentioning

confidence: 99%

Application-specific instruction set processor for SoC implementation of modern signal processing algorithms

Liu

Dickson

McCanny

2005

IEEE Trans. Circuits Syst. I

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Abstract-A novel application-specific instruction set processor (ASIP) for use in the construction of modern signal processing systems is presented. This is a flexible device that can be used in the construction of array processor systems for the real-time implementation of functions such as singular-value decomposition (SVD) and QR decomposition (QRD), as well as other important matrix computations. It uses a coordinate rotation digital computer (CORDIC) module to perform arithmetic operations and several approaches are adopted to achieve high performance including pipelining of the micro-rotations, the use of parallel instructions and a dual-bus architecture. In addition, a novel method for scale factor correction is presented which only needs to be applied once at the end of the computation. This also reduces computation time and enhances performance. Methods are described which allow this processor to be used in reduced dimension (i.e., folded) array processor structures that allow tradeoffs between hardware and performance. The net result is a flexible matrix computational processing element (PE) whose functionality can be changed under program control for use in a wider range of scenarios than previous work. Details are presented of the results of a design study, which considers the application of this decomposition PE architecture in a combined SVD/QRD system and demonstrates that a combination of high performance and efficient silicon implementation are achievable.Index Terms-Application-specific instruction set processor (ASIP), coordinate rotation digital computer (CORDIC) processors, modern signal processing, QR decomposition (QRD), singular-value decomposition (SVD), system on chip (SoC).

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“…Consider a linear array of p uniformly spaced sensors whose outputs are individually weighted and then summed to produce the beamformer output corresponding to the kth desired look direction e (k) (n) = u T (n) w (k) (n); (23) where u(n) is the p-element vector of signal samples received by the array at time instant n, and w (k) (n) is the p-element vector of weights corresponding to the kth desired look direction. Let c (k) be the kth steering vector which represents the kth desired look direction, and (k) be the corresponding beamforming gain which is usually a constant.…”

Section: A Lcmv Adaptive Beamforming Problemmentioning

confidence: 99%

Annihilation-reordering look-ahead pipelined CORDIC-based RLS adaptive filters and their application to adaptive beamforming

Parhi

Deprettere

2000

IEEE Trans. Signal Process.

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The novel annihilation-reordering look-ahead technique is proposed as an attractive technique for pipelining of Givens rotation (or CORDIC) based adaptive lters. Unlike the existing relaxed look-ahead, the annihilation-reordering look-ahead does not depend on the statistical properties of the input samples. It is an exact look-ahead and based on CORDIC arithmetic, which is known to be numerically stable. The conventional look-ahead is based on multiply-add arithmetic. The annihilation-reordering look-ahead technique transforms an orthogonal sequential adaptive ltering algorithm into an equivalent orthogonal concurrent one by creating additional concurrency in the algorithm. Parallelism in the transformed algorithm is explored, and di erent implementation styles including pipelining, block processing, and incremental block processing are presented. Their complexity are also studied and compared. The annihilation-reordering look-ahead is employed to develop ne-grain pipelined QR decomposition based RLS adaptive lters. Both implicit and explicit weight extraction algorithms are considered. The proposed pipelined architectures can be operated at arbitrarily high sample rate without degrading the lter convergence behavior. Stability under nite-precision arithmetic are studied and proved for the proposed architectures. The pipelined CORDIC based RLS adaptive lters are then employed to develop high-speed linear constraint minimum variance (LCMV) adaptive beamforming algorithms. Both QR decomposition based minimum variance distortionless response (MVDR) realization and generalized sidelobe canceller (GSC) realization are presented. The complexity of the pipelined architectures are analyzed and compared. The proposed architectures can be operated at arbitrarily high sample rate, and consist of only Givens rotations which can be scheduled onto CORDIC arithmetic based processors.

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Floating point Cordic

Cited by 29 publications

References 5 publications

Efficient Floating-Point Givens Rotation Unit

Efficient Floating-Point Givens Rotation Unit

Application-specific instruction set processor for SoC implementation of modern signal processing algorithms

Annihilation-reordering look-ahead pipelined CORDIC-based RLS adaptive filters and their application to adaptive beamforming

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