2009 International Conference on Reconfigurable Computing and FPGAs 2009
DOI: 10.1109/reconfig.2009.26
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Floating Point Hardware for Embedded Processors in FPGAs: Design Space Exploration for Performance and Area

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Cited by 7 publications
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“…A similar but larger FPU implementation for the Plasma core was discussed in [35]. It is worth investigating novel implementations that could reduce the size of the floating point logic, for example reusing FP units to also do integer calculations or combining them as in [36].…”
Section: Related Workmentioning
confidence: 99%
“…A similar but larger FPU implementation for the Plasma core was discussed in [35]. It is worth investigating novel implementations that could reduce the size of the floating point logic, for example reusing FP units to also do integer calculations or combining them as in [36].…”
Section: Related Workmentioning
confidence: 99%