FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs

Abstract

A6struct-The field programmable gate-array (FPGA) has become an important technology in VLSI ASIC designs. In the past a few years, a number of heuristic algorithms have been proposed for technology mapping in lookup-table (LUT) based FPGA designs, but none of them guarantees optimal solutions for general Boolean networks and Little is known about how far their solutions are away h m the optimal ones. This paper presents a theoretical breakthrough which shows that the LUT-based FPGA technology mapping problem for depth minimization can be solved optimally in polynomial time. A key step in our algorithm is to compute a minimum height K-feasible cut in a network, which is solved optimally in polynomial time based on network flow computation. Our algorithm also effectively minimizes the number of LUT's by maximizing the volume of each cut and by several post-processing operations. Based on these results, we have implemented an LUT-based FPGA mapping package called FlowMap. We have tested FlowMap on a large set of benchmark examples and compared it with other LUT-based FPGA mapping algorithms for delay optimization, including Chortle-d, MIS-pgadelay, and DAG-Map. FlowMap reduces the LUT network depth by up to 7% and reduces the number of LUT's by up to 50% compared to the three previous methods.

Power-aware technology mapping for LUT-based FPGAs

“…We compare our technology mapper with two publicly available technology mappers: 1) FlowMap [4], which maps circuits in a depth-optimal manner and 2) FlowMap-r [5], which optimizes both depth and area by relaxing the depth optimality on portions of a circuit that are not depthcritical and then performing duplication-free mapping. Additionally, we consider the effect of using various areareducing post-processing routines, including FlowPack (FP) [4], MP-Pack (MP) 1 [15].…”

“…The second term in the square brackets is negative and its intent is similar to the second summation term in (4). By including a replicated node v in a LUT, we "capture" a subset of its fanout connections within the LUT.…”

“…The mapping phase of our algorithm is similar to that of FlowMap [4]. We initialize a FIFO queue to contain all of the primary output nodes.…”

“…An important step in the FPGA CAD flow is technology mapping, which involves transforming a circuit from a generic form into a network of LUTs. LUT-based technology mapping has been studied extensively in recent years, with most research being focused on optimizing the area [3] and/or the depth [4,5] of the mapped circuit. Power represents the third, largely unexplored axis along which an FPGA design should be optimized.…”

Smart Enumeration: A Systematic Approach to Exhaustive Search

“…Table 3 shows benchmarks chosen from the standard ISCAS 85, 89 and 99 sets, with bounds of LUTs for area and latencies -these worst-case results are the initial upper and lower bounds from table 1. The XST, DAOmap [15] and FlowMap [14] results are for each output individually -we remove hardware for other outputs. The bounds improvement results for these benchmarks show runtime and minimal shapes found (software results run on an Intel Xeon 2Ghz processor).…”