Power-aware technology mapping for LUT-based FPGAs

Anderson, James H.; Najm, Farid N.

doi:10.1109/fpt.2002.1188684

Cited by 44 publications

(38 citation statements)

References 18 publications

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“…To show the efficiency of our algorithm, we first design a mapping algorithm with single Vdd, which uses similar cost function as that in DVmap and relaxes the noncritical paths based on cost to achieve better power results. The single-Vdd mapper, named SVmap, shows an advantage over the latest published low-power mapping algorithm Emap [10] and another low power mapper presented in [8]. We then show that our dual-Vdd mapping algorithm DVmap can further improve SVmap by up to 11.6% for power savings.…”

Section: Introductionmentioning

confidence: 84%

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Low-power technology mapping for FPGA architectures with dual supply voltages

Chen

Cong

et al. 2004

Proceedings of the 2004 ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays

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In this paper we study the technology mapping problem of FPGA architectures with dual supply voltages (Vdds) for power optimization. This is done with the guarantee that the mapping depth of the circuit will not increase compared to the circuit with a single Vdd. We first design a single-Vdd mapping algorithm that achieves better power results than the latest published lowpower mapping algorithms. We then show that our dual-Vdd mapping algorithm can further improve power savings by up to 11.6% over the single-Vdd mapper. In addition, we investigate the best low-Vdd/high-Vdd ratio for the largest power reduction among several dual-Vdd combinations. To our knowledge, this is the first work on dual-Vdd mapping for FPGA architectures.

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Section: Introductionmentioning

confidence: 84%

“…There are previous works on technology mapping for low-power FPGA designs, all assuming single Vdd [7,8,9,10]. The basic approach was to hide the nodes of high-switching activity into LUTs so the overall dynamic power was reduced.…”

Section: Introductionmentioning

confidence: 99%

Low-power technology mapping for FPGA architectures with dual supply voltages

Chen

Cong

et al. 2004

Proceedings of the 2004 ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays

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show abstract

“…Both [24] and [25] used this method for mapping to minimize area. The works in [9], [11], and [12] present low-power mappers based on this technique as well. After cut enumeration and arrival time and cost propagation, a cut selection procedure is carried out to cover the entire netlist.…”

Section: A Overviewmentioning

confidence: 99%

“…4) Output Fanout Number: Another factor we consider is the fanout number of the root node of the target cut. This is trying to control node duplication because duplication usually hurts power minimization [9]. In Fig.…”

Section: Calculation Of Cut Costmentioning

confidence: 99%

Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages

Chen

Cong

Dong

et al. 2010

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-This paper presents a technology mapping algorithm for field-programmable gate array architectures with dual supply voltages (Vdds) for power optimization. This is done with the guarantee that the mapping depth of the circuit will not increase compared to the circuit with a single Vdd. This paper also presents an enhanced clustering algorithm that considers dual supply voltages, honoring the dual-Vdd mapping solution. To carry out various comparisons, we first design a single-Vdd mapping algorithm, named SVmap-2, which achieves a 3.8% total power reduction (15.6% dynamic power reduction) over a previously published low-power mapping algorithm, Emap [11]. We then show that our dual-Vdd mapping algorithm, named DVmap-2, can further improve total power savings by 12.8% over SVmap-2, with a 52.7% dynamic power reduction. Compared to the early single-Vdd version SVmap [14], DVmap-2 is 14.3% better for total power reduction. This is achieved through an ideal selection of the low-Vdd/high-Vdd ratio and the consideration of various voltage changing scenarios during the mapping process.Index Terms-Dual-supply voltages, field-programmable gate array (FPGA), power optimization, technology mapping.

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“…There is previous work such as [11], [12], PowerMap [13], PowerMinMap [14], Emap [15], and SVmap/DVmap [16] on low-power FPGA technology mapping. Techniques including bin packing, dynamic programming, greedy algorithm, binate covering, network flow algorithm, and cut-enumeration algorithm have been applied to hide the nodes of high-switching activity into LUTs so the overall dynamic power can be reduced.…”

Section: Seumentioning

confidence: 99%

SETmap: A soft error tolerant mapping algorithm for FPGA designs with low power

Peng¹,

Dong²,

Chen³

2011

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)

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Field programmable gate arrays (FPGAs) are widely used in VLSI applications due to their flexibility to implement logical functions, fast total turn-around time, and low non-recurring engineering cost. The most popular FPGAs in the market are SRAM-based FPGAs. However, as process technologies advance to nanometer-scale regimes, the issue of reliability of devices becomes critical. Soft errors are increasingly becoming a reliability concern because of the shrinking process dimensions. In this thesis, we study the technology mapping problem for FPGA circuits to reduce the occurrence of soft errors under the chip performance constraint and power reduction. Compared to two power-optimization mapping algorithms, SVmap and Emap, respectively, we reduce the single event upset (SEU) rate by 30.5% with a 3.7% power overhead penalty and 50.1% with a 4.7% power overhead penalty using six-input LUTs. When multi-event upset (MEU) occurs, our work reduces the soft error rate by 33% and 31.5% for double bit flips and triple bit flips, respectively, compared to SVmap, and by 52.9% and 50.3% for double bit flips and triple bit flips, respectively, compared to Emap.iii ACKNOWLEDGMENTS

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Power-aware technology mapping for LUT-based FPGAs

Abstract: We present a new power-aware technology mapping technique for LUT-based

Cited by 44 publications

References 18 publications

Low-power technology mapping for FPGA architectures with dual supply voltages

Low-power technology mapping for FPGA architectures with dual supply voltages

Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages

SETmap: A soft error tolerant mapping algorithm for FPGA designs with low power

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