2015
DOI: 10.1088/0957-4484/26/45/455201
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Fluorinated CYTOP passivation effects on the electrical reliability of multilayer MoS2 field-effect transistors

Abstract: We demonstrated highly stable multilayer molybdenum disulfide (MoS2) field-effect transistors (FETs) with negligible hysteresis gap (ΔV(HYS) ∼ 0.15 V) via a multiple annealing scheme, followed by systematic investigation for long-term air stability with time (∼50 days) of MoS2 FETs with (or without) CYTOP encapsulation. The extracted lifetime of the device with CYTOP passivation in air was dramatically improved from 7 to 377 days, and even for the short-term bias stability, the experimental threshold voltage s… Show more

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Cited by 51 publications
(36 citation statements)
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“…Thereafter, a 25 nm thick layer of Au was evaporated using egun evaporators, followed by lifting off on a photo lithographically patterned area, forming the source/drain electrodes. After an evaluation of the electrical properties of the fabricated MoS 2 FETs, selected driver TFTs were coated by CYTOP (CTL-809M, Asahi Glass Co., Ltd), followed by annealing at 150 o C in a glove box (~Ar ambient) for an inter-layer dielectric (ILD) [16]. Additional 100 nm thick Au layers were defined on specific areas of the driver TFTs, except for the contact region of the S/D electrodes.…”
Section: Methodsmentioning
confidence: 99%
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“…Thereafter, a 25 nm thick layer of Au was evaporated using egun evaporators, followed by lifting off on a photo lithographically patterned area, forming the source/drain electrodes. After an evaluation of the electrical properties of the fabricated MoS 2 FETs, selected driver TFTs were coated by CYTOP (CTL-809M, Asahi Glass Co., Ltd), followed by annealing at 150 o C in a glove box (~Ar ambient) for an inter-layer dielectric (ILD) [16]. Additional 100 nm thick Au layers were defined on specific areas of the driver TFTs, except for the contact region of the S/D electrodes.…”
Section: Methodsmentioning
confidence: 99%
“…An n-type silicon wafer with heavy phosphorus doping (U~0.005 ohmxcm) was used as a starting substrate, playing the role of gate electrode, followed by thermal oxidation to create a gate insulator for the multi-layered MoS 2 FETs. Multilayers of molybdenum disulfide (MoS 2 ) were mechanically exfoliated from bulk MoS 2 crystals (SPI Supplies, 429ML-AB) and transferred onto Si substrates, with thermal oxide (~10 nm) as a gate insulator, by using poly dimethylsioxane (PDMS) elastomer (for the method, see [16]). After confirming the thickness of the multi-layered MoS 2 using AFM analysis, as shown in Fig.…”
Section: Introductionmentioning
confidence: 99%
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“…Absorbed gaseous molecules and moisture can act as a charge trap site [15]. To prevent the molecules being absorbed, we adopted flourinated polymer (CYTOP; CTL-809  M , Asahi Glass Co., Ltd) passivation so that the drift of the drain current in MoS 2 FETs was reduced greatly [16]. Therefore, the backside of the WSe 2 flake was encapsulated by the CYTOP with typical spin coating process.…”
Section: Methodsmentioning
confidence: 99%
“…After confirming that the smoothened aramid paper is suitable for organic device fabrication, we fabricated OFETs on top of the aramid paper substrate. Cytop was used as the gate dielectric because of its high hydrophobicity, which leads to fewer trapping sites through the channel . We used dinaphtho[2,3‐ b :2′,3′‐f]thieno[3,2‐ b ]thiophene (DNTT) as the organic semiconducting layer because it possesses good air stability with high field‐effect mobility .…”
Section: General Electrical Performance and Extracted Parameters Frommentioning
confidence: 99%