The experimental and modeling study of bias-stress-induced threshold voltage instabilities in amorphous indium-gallium-zinc oxide thin film transistors is reported. Positive stress results in a positive shift in the threshold voltage, while the transfer curve hardly moves when negative stress is induced. The time evolution of threshold voltage is described by the stretched-exponential equation, and the shift is attributed to the electron injection from the channel into interface/dielectric traps. The stress amplitudes and stress temperatures are considered as important factors in threshold voltage instabilities, and the stretched-exponential equation is well fitted in various bias temperature stress conditions.

We have investigated the static and dynamic bias stress-induced charge trapping and detrapping phenomenon in amorphous indium-gallium-zinc oxide thin film transistors. It is observed that the charges trapped after electron injection in the interface and bulk traps are unstable and slowly decay over time. The stretched-exponential equation, which can be derived based on the trapping/detrapping of charges to/from existing traps and continuous redistribution of charges in bulk dielectrics, is successfully applied in fitting the time dependence of the threshold voltage shift during the stress and recovery phases under dynamic stresses. The characteristic time constants decrease with increasing temperature and drain bias during the recovery phase. Under dynamic stresses with various frequencies, the threshold voltage shift strongly depends on the frequency of dynamic stresses, i.e., a high frequency stress results in a small threshold voltage shift and a long lifetime. The stress-induced threshold shift phenomenon is observed to be relieved after a long-time low temperature post thermal annealing process and device passivation with an aluminum oxide layer.

A comparative study was made of the performance and electrical instabilities in amorphous indium-gallium-zinc oxide (a-IGZO) thin film transistors with Al2O3 and Al2O3/SiNx gate dielectrics. Steeper subthreshold slope is observed in Al2O3 devices, which shows that the density of trap states at the interface of a-IGZO/Al2O3 is lower than that of a-IGZO/SiNx. Under high bias-stresses, a larger degradation is observed in Al2O3/SiNx devices. The device degradation for both devices are mainly attributed to the charge trapping phenomenon, but the different time dependence of threshold voltage shift shows that trapped electrons are more easily redistributed inside the Al2O3 dielectrics.

We investigate the effects of ambient atmosphere on the electrical performance of p-type tin monoxide (SnO) thinfilm transistors (TFTs), and present the effective method for the passivation of SnO TFTs using a SU-8 organic layer. The experimental data shows that the SnO TFTs without a passivation layer suffer from the electrical performance degradation under humid environments, which implies that the formation of the passivation layer is necessary in p-type SnO TFTs for the stable operation of the devices. The SU-8 organic layer was successfully incorporated as a passivation layer of SnO TFTs. The SnO TFTs with a SU-8 passivation layer exhibit very similar transfer characteristics with those without a passivation layer, and show much improved long-term durability and bias stress stability compared with the SnO TFTs without a passivation layer under air environments.Index Terms-P-type SnO TFTs, SU-8 passivation layer, humidity, long-term durability, bias stress stability.

We demonstrated highly stable multilayer molybdenum disulfide (MoS2) field-effect transistors (FETs) with negligible hysteresis gap (ΔV(HYS) ∼ 0.15 V) via a multiple annealing scheme, followed by systematic investigation for long-term air stability with time (∼50 days) of MoS2 FETs with (or without) CYTOP encapsulation. The extracted lifetime of the device with CYTOP passivation in air was dramatically improved from 7 to 377 days, and even for the short-term bias stability, the experimental threshold voltage shift, outstandingly well-matched with the stretched exponential function, indicates that the device without passivation has approximately 25% larger the barrier distribution (ΔE(B) = k(B)T(o)) than that of a device with passivation. This work suggests that CYTOP encapsulation can be an efficient method to isolate external gas (O2 and H2O) effects on the electrical performance of FETs, especially with low-dimensional active materials like MoS2.