Flying and decoupling capacitance optimization for area-constrained on-chip switched-capacitor voltage regulators

Early-Stage Planning of Switched-Capacitor Converters in a Heterogeneous Chip

“…A lot of prior works have investigated the optimization of the SCC design to achieve better energy efficiency, and have proposed techniques such as tuning the size of flying capacitors, operating frequency and switch width etc. [17], [21]- [26]. However, there are limited works on optimizing the energy efficiency of SCCs in a holistic way in a multi-core chip.…”

“…In [9], the authors improve the overall energy efficiency of many-core system by dynamically adapting the switching frequency f sw of each SCC to the specific output load. The authors in [26] aim to not only achieve the highest energy efficiency but also suppress supply noise by optimizing the allocation of limited die area between flying capacitance and decoupling capacitance. In [19], the authors propose a system level efficiency model which characterizes the number, size and distribution of the SCCs, and they solve the optimization problem by mathematical optimization methods.…”