Focal-Plane Scale Space Generation with a 6T Pixel Architecture

Oliveira, Fernanda D. V. R.; Gomes, Jonas; Carmona-Galán, Ricardo; Fernández-Berni, Jorge; Rodríguez-Vázquez, Á.

doi:10.2352/issn.2470-1173.2016.12.imse-270

Cited by 2 publications

(4 citation statements)

References 15 publications

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“…3. An n-channel transistor can be used as a switch, resulting in a pixel with six transistors [21]. Pixel operation starts by resetting the floating diffusion nodes.…”

Section: Proposed Pixel Implementationmentioning

confidence: 99%

“…With the proposed hardware, it is possible to generate a scale space that can be used by the SIFT without a significant performance drop [21]. First, we capture the image and group the pixels into 2×2 pixel blocks.…”

Section: Case Study: Sift Algorithmmentioning

confidence: 99%

“…The resulting standard deviation is σ 2 = σ 2 1 + σ 2 f ilter = 0.707. The ratio of the standard deviations of adjacent scale-space filters must be kept constant [21], k = σ 2 /σ 1 = √ 2. Consequently, the next image must be the result of filtering with a kernel with standard deviation equal to k · σ 2 = 1.…”

Section: Case Study: Sift Algorithmmentioning

confidence: 99%

See 2 more Smart Citations

Gaussian Pyramid: Comparative Analysis of Hardware Architectures

Oliveira

Gomes

Fernández-Berni

et al. 2017

IEEE Trans. Circuits Syst. I

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Abstract-The paper addresses a comparison of architectures for hardware implementation of Gaussian image pyramids. Main differences between architectural choices are in the sensor frontend. One side is for architectures consisting of a conventional sensor that delivers digital images and which is followed by digital processors. The other side is for architectures employing a non-conventional sensor with per-pixel embedded pre-processing structures for Gaussian spatial filtering. This later choice belongs to the general category of "artificial retina" sensors which have been for long claimed as potentially advantageous for enhancing throughput and reducing energy consumption of vision systems. These advantages are very important in the internet of things context, where imaging systems are constantly exchanging information. The paper attempts to quantify these potential advantages within a design space in which the degrees of freedom are the number and type of ADCs (single-slope, SAR, cyclic, Σ∆ and pipeline), and the number of digital processors. Results show that speed and energy advantages of pre-processing sensors are not granted by default and are only realized through proper architectural design. The methodology presented for the comparison between focal-plane and digital approaches is a useful tool for imager design, allowing for the assessment of focal-plane processing advantages.

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“…3. An n-channel transistor can be used as a switch, resulting in a pixel with six transistors [21]. Pixel operation starts by resetting the floating diffusion nodes.…”

Section: Proposed Pixel Implementationmentioning

confidence: 99%

Section: Case Study: Sift Algorithmmentioning

confidence: 99%

See 1 more Smart Citation

Gaussian Pyramid: Comparative Analysis of Hardware Architectures

Oliveira

Gomes

Fernández-Berni

et al. 2017

IEEE Trans. Circuits Syst. I

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“…The back substrate was exposed to the incident light instead of the front metal gate side, which can greatly reduce the reflection on the surface by metal and increase the photon flux that can approach the sensitive region. The pixel structure varies with design and applications, apart from the structures introduced above, pixels with five transistors (5T) [50,51], six transistors [52,53], or even more [54] have been proposed.…”

Section: Charge-coupled Device (Ccd)mentioning

confidence: 99%

Electrochemical and optical CMOS sensors design for biochemical detection

Jiang¹

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The contributions of the co-authors are as follows:• Prof Yu provided the initial ideal and edited the manuscript drafts.• Prof. Zhang and Prof. Feng revised the manuscript drafts.• I prepared the manuscript drafts, designed the ISFET pixel array with the pH-TVC readout circuit, worked in the full chip integration, built the testing system, and performed all the measurements, experiments, and data processing.

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Focal-Plane Scale Space Generation with a 6T Pixel Architecture

Abstract: Abstract

Cited by 2 publications

References 15 publications

Gaussian Pyramid: Comparative Analysis of Hardware Architectures

Gaussian Pyramid: Comparative Analysis of Hardware Architectures

Electrochemical and optical CMOS sensors design for biochemical detection

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