Fog Acceleration through Reconfigurable Devices

Barbieri, Samuele; Casasopra, Fabiola; Brondolin, Rolando; Santambrogio, Marco D.

doi:10.1109/rtsi.2019.8895567

Cited by 3 publications

(3 citation statements)

References 9 publications

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“…Nonetheless, a further increment in the number of boards of the distributed system would lead to the saturation of the fully connected block, that cannot support more than 720 chunks/s. With three replicas of the convolutional block, the throughput gain goes down to 10% with respect to three separate PYNQs in parallel performing the computations of the full BNN (the respective [13] framework, an event-based system that we modified to support jobs and pipelines. In particular, a job has been implemented as a task accepting data from an input queue that is killed after all the data has been processed.…”

Section: ) Resource Utilizationmentioning

confidence: 99%

BNNsplit: Binarized Neural Networks for embedded distributed FPGA-based computing systems

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Stornaiuolo

et al. 2020

2020 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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In the past few years, Convolutional Neural Networks (CNNs) have seen a massive improvement, outperforming other visual recognition algorithms. Since they are playing an increasingly important role in fields such as face recognition, augmented reality or autonomous driving, there is the growing need for a fast and efficient system to perform the redundant and heavy computations of CNNs. This trend led researchers towards heterogeneous systems provided with hardware accelerators, such as GPUs and FPGAs. The vast majority of CNNs is implemented with floating-point parameters and operations, but from research, it has emerged that high classification accuracy can be obtained also by reducing the floating-point activations and weights to binary values. This context is well suitable for FPGAs, that are known to stand out in terms of performance when dealing with binary operations, as demonstrated in FINN, the state-of-theart framework for building Binarized Neural Network (BNN) accelerators on FPGAs. In this paper, we propose a framework that extends FINN to a distributed scenario, enabling BNNs implementation on embedded multi-FPGA systems.

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Section: ) Resource Utilizationmentioning

confidence: 99%

BNNsplit: Binarized Neural Networks for embedded distributed FPGA-based computing systems

Fiscaletti

Speziali

Stornaiuolo

et al. 2020

2020 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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“…Fog Acceleration through Reconfigurable Devices (FARD) [4] is a fog computing distributed system designed to allow seamless cooperation across heterogeneous fog computing nodes. Inside FARD, two different aspects are coexisting: hardware acceleration and distributed run-time management.…”

Section: B Fardmentioning

confidence: 99%

“…In this work, we propose an analysis of the hardware resource usage while modifying the CNN splitting point and we describe how FARD [4], a framework to implement fog computing distributed system accelerators, is modified to deal with this kind of applications. This is a continuation of our previous work BNNsplit [5], where we explored splitting strategies for Xilinx FINN BNNs [6].…”

Section: Introductionmentioning

confidence: 99%

Hardware resources analysis of BNNs splitting for FARD-based multi-FPGAs Distributed Systems

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Stornaiuolo

et al. 2020

2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)

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FPGAs have proven to be valid architectures to accelerate the inference phase of Convolutional Neural Networks (CNNs). State-of-the-art works also demonstrated that it is possible to take advantage of a distributed FPGA-base system to improve performance, power consumption and scalability of such algorithms. However, the hardware resource usage, communication, and the nodes management become main aspects when dealing with an embedded distributed scenario. In this context, FINN optimizes the FPGA-based CNNs with binarization and FARD is a framework that allows the acceleration of fog computing-based application with FPGAs. In this work, we present how to extend FARD to deal with job-based applications rather than the event-based fog computing scenario. In particular, we analyzed two PYNQ-Z1 connected each other and we implemented a distributed BNN algorithm based on FINN's CnvW2A2. Results show how hardware resources vary according to the division of the network when splitting after each convolutional layer.

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Plaster: an Embedded FPGA-based Cluster Orchestrator for Accelerated Distributed Algorithms

Farinelli

Vincenti

Damiani

et al. 2021

2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)

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Fog Acceleration through Reconfigurable Devices

Cited by 3 publications

References 9 publications

BNNsplit: Binarized Neural Networks for embedded distributed FPGA-based computing systems

BNNsplit: Binarized Neural Networks for embedded distributed FPGA-based computing systems

Hardware resources analysis of BNNs splitting for FARD-based multi-FPGAs Distributed Systems

Plaster: an Embedded FPGA-based Cluster Orchestrator for Accelerated Distributed Algorithms

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