FOI FinFET with ultra-low parasitic resistance enabled by fully metallic source and drain formation on isolated bulk-fin

Zhang, Qingzhu; Yin, Huaxiang; Luo, Jun; Yang, Hong; Meng, Lingkuan; Li, Yudong; Wu, Zhenhua; Zhang, Yanbo; Zhang, Yongkui; Qin, Changliang; Li, Junjie; Gao, Jianfeng; Wang, Guilei; Xiong, Wentao; Xiang, Jinjuan; Zhou, Zikai; Shujian, Mao; Xu, Gaobo; Liu, Jinbiao; Qu, Yang; Yang, Tao; Li, Junfeng; Xu, Qing; Jiang, Yan; Zhu, Huilong; Zhao, Chao; Ye, Tianchun

doi:10.1109/iedm.2016.7838438

Cited by 34 publications

(18 citation statements)

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“…As a result, the most promising transistor architectures may be fin-on-insulator (FOI) Fin Field-Effect Transistor (FinFET) [ 8 , 9 , 10 , 11 ], scalloped fin FinFET [ 12 ], and NW field effect transistors (FETs) [ 13 , 14 , 15 ]. These new transistor designs have shown better control of short channel effects (SCEs), low leakage junctions, and high carrier mobility.…”

Section: Introductionmentioning

confidence: 99%

“…One interesting property of FOI FinFET is the advantage that bulk FinFET and SOI technologies are merged in these transistors for a better platform in the technology roadmap. Moreover, a recent report from IMECAS has demonstrated a simple and cost effective fully metallic source and drain (MSD) process for FOI FinFETs with a gate length of 20 nm where I on reaches up to 547 μA/μm and 486 μA/μm for NMOS and PMOS, respectively [ 9 ]. These results give an excellent potential solution for future nano-scale transistors.…”

Section: Introductionmentioning

confidence: 99%

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State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

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The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

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“…Thus, new device structures, new materials, and new integration approaches have to provide new solutions. Therefore, novel promising device architectures like fin-on-insulator (FOI) FinFET [8,9,10,11], scalloped fin FinFET [12], nanowire (NW) FETs, and the stacked NW device [13,14,15] have demonstrated great improvement for short channel effects (SCEs), leakage control, and higher electron and whole mobility. The fin-on-insulator (FOI) FinFET, fabricated on the bulk Si substrate with a special process takes both advantages of bulk FinFET and SOI technologies.…”

Section: Introductionmentioning

confidence: 99%

Miniaturization of CMOS

Radamson

Zhang

et al. 2019

Micromachines

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When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today’s 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy. A focus has been on methodologies, challenges, and difficulties when ITRS approaches the end. The discussions extend to new channel materials beyond the Moore era.

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“…Since p-type FinFET device can achieve large programming gate current at low power consumption and provides high-speed programming owing to the large probability of electron injection, 19,20 the investigation focuses on p-channel memory device. The ultra-small SOI-liked fin structure is formed by self-aligned spacer image transfer (SIT) patterning, notched-fin etch and then a low rate linear oxidation process, followed by isolation oxide deposition, 10,11 as shown in Figs. 2a, 2b, 2c.…”

Section: Fabrication Processmentioning

confidence: 99%

“…[6][7][8][9] Recently a novel type of FinFET structure, named as fin-on-insulator (FOI) FinFET has been proposed. 10,11 By adopting FOI structure, subsurface leakage paths in FinFETs are eliminated, the drain-induced barrier lowering (DIBL) is further reduced due to physically isolated fin channel. It is expected that this new device structure can potentially be used for NOR-type flash memory to make it more scalable and reliable.…”

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confidence: 99%

Fabrication and Characterization of p-Channel Charge Trapping Type FOI-FinFET Memory with MAHAS Structure

Hou¹,

Zhang²,

Yin³

et al. 2017

ECS J. Solid State Sci. Technol.

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A type of p-channel fin-on-insulator (FOI) FinFET charge trapping memory devices with HfO 2 charge trapping layer, Al 2 O 3 tunneling layer and blocking layers along with [TiN/W] metal gate (Metal/Al 2 O 3 /HfO 2 /Al 2 O 3 /Si, named as MAHAS in short) have been successfully fabricated. It is found that the new non-volatile memory, named in FOI-MAHAS memory shows better performance as compared with counterparts reported earlier owing to the adoption of p-type FOI channel and specific high-κ dielectrics. The static DC electrical characteristics of the fabricated memory devices including threshold voltage, subthreshold slope, gate breakdown voltage (BV g ), source-drain breakdown voltage (BV DS ) and memory characteristics such as program/erase (P/E) speed, memory window, endurance, and data retention at room temperature with different P/E approaches have been systematically investigated. A larger memory window, lower P/E voltages, improved P/E speed, as well as good data retention and endurance characteristics with band-to-band hot-electron (BBHE) programming are experimentally obtained. The developed p-channel FOI-MAHAS charge trapping memory is promising for the future nano-scaled NOR-type flash memory applications. It is well known that further scaling-down of the conventional bulk planar metal-oxide-semiconductor field-effect transistor (MOSFET) type NOR flash memory becomes very difficult because of the enhanced short-channel effect (SCE) induced by decreased gate control over channel region with the shrinkage of distance between source and drain. It is noteworthy that further scaling of planar NOR-type memory device faces the theoretical limit of source-drain breakdown voltage (BV DS ) which corresponds to the silicon (Si) and silicon dioxide (SiO 2 ) conduction band offset (3.2 eV). Thus, the scaled planar NOR-type flash memories with gate length (L g ) smaller than 100 nm are very difficult to fabricate.1-4 On the other hand, three-dimensional (3D) channel devices, such as fin field-effect transistors (FinFET) or fin-channel tri-gate (TG) device provide excellent SCE immunity thanks to the strong electrostatic controllability of the multiple gates. 5 Moreover, threshold voltage (V th ) variability in the FinFET or TG devices is much smaller than that in the conventional bulk planar MOSFETs because V th variation induced by the random dopant fluctuation (RDF) is negligible in FinFET or TG devices owing to the undoped fin-channels. Additionally, earlier study has shown that the electric field gets significantly enhanced in the curve part of the fin, thus the carrier injection rate from the channel gets substantially increased. As a result, the program and erase speeds of FinFET memory devices get obviously increased with respect to planer counterparts. [6][7][8][9] Recently a novel type of FinFET structure, named as fin-on-insulator (FOI) FinFET has been proposed.10,11 By adopting FOI structure, subsurface leakage paths in FinFETs are eliminated, the drain-induced barrier lowering (DIBL) is further reduced ...

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FOI FinFET with ultra-low parasitic resistance enabled by fully metallic source and drain formation on isolated bulk-fin

Cited by 34 publications

References 2 publications

State of the Art and Future Perspectives in Advanced CMOS Technology

State of the Art and Future Perspectives in Advanced CMOS Technology

Miniaturization of CMOS

Fabrication and Characterization of p-Channel Charge Trapping Type FOI-FinFET Memory with MAHAS Structure

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