Formal system‐level design space exploration

Abstract

SUMMARYDIPLODOCUS is a UML profile intended for the modeling and the formal verification of real‐time and embedded applications commonly executed on complex Systems‐on‐Chip. DIPLODOCUS implements the Y‐chart approach, that is, application and HW architecture (e.g., CPUs, bus, memories) are first described independently and are subsequently related to each other in a mapping stage. Abstract tasks and communication primitives are therefore mapped onto platform elements like buses and CPUs. DIPLODOCUS endows all models with a formal semantics, thereby paving the way for formal proofs both before and after mapping. More concretely, application, architecture, and mapping models can be edited in TTool – an open‐source toolkit – using UML diagrams. Then, pre‐mapping or post‐mapping UML models may be automatically transformed into a LOTOS‐based representation. This specification is in turn amenable to model‐checking techniques to evaluate properties of the system, for example, safety, schedulability, and performance properties. A smart card system serves as case study to illustrate the formal verification capabilities of DIPLODOCUS. Copyright © 2012 John Wiley & Sons, Ltd.

DiplodocusDF, a Domain-Specific Modelling Language for Software Defined Radio Applications

“…3) Formal verification by transforming the mapped application into its formal representation. The extended language was specified such that retains the support of DIPLODOCUS [7] to formally verify functional or nonfunctional properties. 4) Code generation for final representation, either SystemC code or C-language code.…”

“…We extended DIPLODOCUS [7], a MDD methodology for formal design exploration, to DiplodocusDF, a MDD methodology for the domain of SDR: (1) to support the description of waveforms, which are based on data-flow, while DIPLODOCUS was only suitable for control-based applications. (2) to support the particularities of novel SDR architectures.…”

Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design

“…The HW/SW Partitioning phase of our methodology intends to model the abstract, high-level functionality of a system (Knorreck et al, 2013). It follows the Y-chart approach, first modeling the abstract functional tasks, candidate architectures, and then finally mapping tasks to the hardware components (Kienhuis et al, 2002).…”

Special Issue Editorial: New technologies of distributed systems

“…The paper of Daniel Knorreck et al [6] defines a UML profile intended for the modeling and the formal verification of real-time and embedded applications commonly executed on complex Systems-on-Chip. Abstract tasks and communication primitives are mapped onto platform elements such as buses and CPUs.…”