Formal verification of out-of-order execution using incremental flushing

Skakkebæk, Jens U.; Jones, Robert B.; Dill, David L.

doi:10.1007/bfb0028737

Cited by 38 publications

(27 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…We have previously proposed incremental flushing, an extension to the Burch and Dill flushing approach that inductively empties the buffer in smaller proof steps [12]. We have applied it to automate part of the verification process of out-of-order designs.…”

Section: Distribution Unlimitedmentioning

confidence: 99%

“…We use the same simple model of an out-of-order execution core to illustrate our approach that we used previously [12]. Although this example is not representative of industrial-scale designs, it captures essential features of out-oforder architectures: large queuing buffers, resource allocation within the buffers, and data-path scheduling of execution resources.…”

Section: Distribution Unlimitedmentioning

confidence: 99%

“…We extend the incremental-flushing approach presented in [12] to overcome this problem. Rather than flushing the entire pipeline directly, a set of smaller, inductive flushing steps is performed.…”

Section: Sai-isa Equivalence For Every Completed Instruction Sequencementioning

confidence: 99%

“…Several techniques for formally verifying out-of-order microprocessor designs using theorem proving have recently been suggested [4,[10][11][12]. These techniques all use some form of intermediate abstraction to bridge the gap in abstraction level between the implementation and the specification, as defined by an instructionset architecture (ISA).…”

Section: Introductionmentioning

confidence: 99%

“…The verification discussed in this paper uses a model with unbounded buffers. 4 The Approach As in [12], the goal of our approach is to prove that the out-of-order implementation IMPL (as described by an HDL model) satisfies the ISA model. We define d~i to be the implementation next-state function, which takes an initial state qt and an input instruction i and returns a new state q'i, e.g., q'i = Si(qt,i).…”

mentioning

confidence: 99%

See 4 more Smart Citations

Reducing Manual Abstraction in Formal Verification of Out- of- Order Execution

Jones

Skakkebæk

Dill

1998

Formal Methods in Computer-Aided Design

Self Cite

View full text Add to dashboard Cite

Abstract. Several methods have recently been proposed for verifying processors with out-of-order execution. These methods use intermediate abstractions to decompose the verification process into smaller steps. Unfortunately, the process of manually creating intermediate abstractions is very laborious. We present an approach that dramatically reduces the need for an intermediate abstraction, so that only the scheduling logic of the implementation is abstracted. After the abstraction, we apply an enhanced incremental-flushing approach to verify the remaining circuitry by comparing the processor description against itself in a slightly simpler configuration. By induction, we demonstrate that any reachable configuration is equivalent to the simplest possible configuration. Finally, we prove correctness on the simplest configuration. The approach is illustrated with a simple example of an out-of-order execution core.

show abstract

Section: Distribution Unlimitedmentioning

confidence: 99%

Section: Distribution Unlimitedmentioning

confidence: 99%

Section: Sai-isa Equivalence For Every Completed Instruction Sequencementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

mentioning

confidence: 99%

See 3 more Smart Citations

Reducing Manual Abstraction in Formal Verification of Out- of- Order Execution

Jones

Skakkebæk

Dill

1998

Formal Methods in Computer-Aided Design

Self Cite

View full text Add to dashboard Cite

show abstract

A Framework for Microprocessor Correctness Statements

Aagaard

Cook²,

Day³

et al. 2001

Lecture Notes in Computer Science

Self Cite

View full text Add to dashboard Cite

Most verifications of out-of-order microprocessors compare state-machine-based implementations and specifications, where the specification is based on the instruction-set architecture. The different efforts use a variety of correctness statements, implementations, and verification approaches. We present a framework for classifying correctness statements about safety that is independent of implementation representation and verification approach. We characterize the relationships between the different statements and illustrate how existing and classical approaches fit within this framework.

show abstract

Verifying a Simple Pipelined Microprocessor Using Maude

Harman

2002

Recent Trends in Algebraic Development Techniques

View full text Add to dashboard Cite

Abstract. We consider the verification of a simple pipelined microprocessor in Maude, by implementing an equational theoretical model of systems. Maude is an equationally-based language, with an efficient term rewriting implementation, and effective meta-level tools. Microprocessors and other systems are modelled as iterated maps operating in time over some state-set, and are related by means of data and abstraction maps, and correctness is reduced to state exploration by the choice of an appropriate initialisation function, ensuring/enforcing consistency of the initial state.

show abstract

Formal verification of out-of-order execution using incremental flushing

Cited by 38 publications

References 14 publications

Reducing Manual Abstraction in Formal Verification of Out- of- Order Execution

Reducing Manual Abstraction in Formal Verification of Out- of- Order Execution

A Framework for Microprocessor Correctness Statements

Verifying a Simple Pipelined Microprocessor Using Maude

Contact Info

Product

Resources

About