Formalizing Timing Diagram Requirements in Discrete Duration Calculus

Abstract

Several temporal logics have been proposed to formalise timing diagram requirements over hardware and embedded controllers. These include LTL [CF05], discrete time MTL [AH93] and the recent industry standard PSL [EF16]. However, succintness and visual structure of a timing diagram are not adequately captured by their formulae [CF05].Interval temporal logic QDDC is a highly succint and visual notation for specifying patterns of behaviours [Pan00]. In this paper, we propose a practically useful notation called SeCeNL which enhances negation free fragment of QDDC with features of nominals and limited liveness. We show that timing diagrams can be naturally (compositionally) and succintly formalized in SeCeNL as compared with PSL-Sugar and MTL. We give a linear time translation from timing diagrams to SeCeNL. As our second main result, we propose a linear time translation of SeCeNL into QDDC. This allows QDDC tools such as DCVALID [Pan00,Pan01] and DCSynth to be used for checking consistency of timing diagram requirements as well as for automatic synthesis of property monitors and controllers. We give examples of a minepump controller and a bus arbiter to illustrate our tools. Giving a theoretical analysis, we show that for the proposed SeCeNL, the satisfiability and model checking have elementary complexity as compared to the nonelementary complexity for the full logic QDDC.

Specification and Optimal Reactive Synthesis of Run-time Enforcement Shields

“…A tool DCSynth implements the synthesis method. Logic QDDC [13,12,11] with its interval logic modalities, threshold counting constraints, regular expression like constructs and second-order quantification over temporal variables provides a very rich vocabulary to specify both the system requirements and the deviation constraints. Logic QDDC is a discrete time version of Duration Calculus proposed by Zhou, Hoare and Ravn [5,4] with known automata theoretic decision and model checking procedures [13,3,17,10].…”

“…It gives minimal, deterministic automaton (DFA) for the formula D. We omit the details here. However, the reader may refer to several papers on QDDC for detailed description and examples of QDDC specifications as well as its model checking tool DCVALID [13,11,12].…”

“…As our first main contribution, we propose a logical specification notation for hard deviation constraints using the formulas of an interval temporal logic QDDC. This logic allows us to succinctly and modularly specify regular properties [13,11,12]. With its counting constructs and interval based modalities, it can be used to conveniently specify both the correctness requirement REQ(I, O) as well as the hard deviation constraint HDC.…”

Logical specification and uniform synthesis of robust controllers

“…It gives minimal, deterministic automaton (DFA) for the formula D. We omit the details here. However, the reader may refer to several papers on QDDC for detailed description and examples of QDDC specifications as well as its model checking tool DCVALID [11][12][13].…”

“…Such properties hold intermittently in the behaviour. QDDC is a highly succinct and powerful logic for specifying regular properties [11]. Formally, QDDC has the expressive power of regular languages.…”