In reactive controller synthesis, a number of implementations (controllers) are possible for a given specification because of incomplete nature of specification. To choose the most desirable one from the various options, we need to specify additional properties which can guide the synthesis. In this paper, We propose a technique for guided controller synthesis from regular requirements which are specified using an interval temporal logic QDDC. We find that QDDC is well suited for guided synthesis due to its superiority in dealing with both qualitative and quantitative specifications. Our framework allows specification consisting of both hard and soft requirements as QDDC formulas. We have also developed a method and a tool DCSynth, which computes a controller that invariantly satisfies the hard requirement and it optimally meets the soft requirement. The proposed technique is also useful in dealing with conflicting i.e., unrealizable requirements, by making some of the them as soft requirements. Case studies are carried out to demonstrate the effectiveness of the soft requirement guided synthesis in obtaining high quality controllers. The quality of the synthesized controllers is compared using metrics measuring both the guaranteed and the expected case behaviour of the controlled system. Tool DCSynth facilitates such comparison. This paper introduces a tool DCSynth which allows synthesis of controllers from regular properties (QDDC formulas). The specification in DCSynth is a tuple (I, O, D h , D s ), where D h and D s are QDDC formulas over a set of input and output propositions (I, O). Here, D h and D s are the hard and the soft requirement, respectively 1 . We use the term supervisor for a non-blocking Mealy machine which may non-deterministically produce one or more outputs for each input. A supervisor may be refined to a sub-supervisor by resolving (pruning) the non-determinstic choice of outputs (the sub-supervisor may use additional memory for making the choice.) We define a determinism ordering on supervisors in the paper. A controller is a deterministic supervisor. Ramadge and Wonham [25,26] investigated the synthesis of the maximally permissive supervisor for a regular specification. The maximally permissive supervisor is a unique supervisor, which encompasses all the behaviors invariantly satisfying the specified regular property (See Definition 6). The well known safety synthesis algorithm applied to the DFA for D h gives us the maximally permissive supervisor M P S(D h ) [10]. If no such supervisor exists, the specification is reported as unrealizable.Any controller obtained by arbitrarily resolving the nondeterministic choices for outputs in M P S(D h ) is correct-by-construction. This results in several controllers with distinct behaviours (as shown by previous example). Thus, only correct-by-construction synthesis is not sufficient [3]. Some form of guidance must be provided to the synthesis method to choose among the possible controllers. We use the soft requirements to provide such guidance. Ou...

Several temporal logics have been proposed to formalise timing diagram requirements over hardware and embedded controllers. These include LTL [CF05], discrete time MTL [AH93] and the recent industry standard PSL [EF16]. However, succintness and visual structure of a timing diagram are not adequately captured by their formulae [CF05].Interval temporal logic QDDC is a highly succint and visual notation for specifying patterns of behaviours [Pan00]. In this paper, we propose a practically useful notation called SeCeNL which enhances negation free fragment of QDDC with features of nominals and limited liveness. We show that timing diagrams can be naturally (compositionally) and succintly formalized in SeCeNL as compared with PSL-Sugar and MTL. We give a linear time translation from timing diagrams to SeCeNL. As our second main result, we propose a linear time translation of SeCeNL into QDDC. This allows QDDC tools such as DCVALID [Pan00,Pan01] and DCSynth to be used for checking consistency of timing diagram requirements as well as for automatic synthesis of property monitors and controllers. We give examples of a minepump controller and a bus arbiter to illustrate our tools. Giving a theoretical analysis, we show that for the proposed SeCeNL, the satisfiability and model checking have elementary complexity as compared to the nonelementary complexity for the full logic QDDC.

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