Formation and characterization of high-performance silicon thin-film transistors with and without location-controlled grain boundary

Abstract

This paper reports the demonstration of structural effects on excimer laser crystallization (ELC) for the Si strip with a recessed-channel structure on the silicon nitride under-layer (RCS-ULN). We revealed that a single location-controlled grain boundary (GB) oriented normal to the Si strip in the middle site without any other GB in the recessed region can be attained via ELC for the RCS-ULN structures with a short recessed region between neighboring long thick regions in a narrow Si strip. This can be attributed to the effective production of a significant 2D lateral thermal gradient in the recessed region and neighboring thick regions. Consequently, the RCS-ULN TFTs fabricated at the position one-half of such an optimal recessed region can achieve a superior field-effect mobility of 670 cm 2 V −1 • s −1 with minor performance variations since the single-crystal-like Si channel has been adopted.

Nanowire single-crystal grain and single grain boundary silicon field effect transistors for direct electrical characterization of grain boundaries

“…In the ELA poly-Si thin film, grain boundaries (GBs) played as barrier potentials to prevent the channel current flow. 8,9) Studying the characterization of GBs and their effect on FETs' performance has attracted much attention along with developing poly-Si thin films with large crystal grains and single-grains (s-Gs) on transparent substrates. [10][11][12][13][14][15] Continuous-wave laser lateral crystallization (CLC) with a diode-pumped solid-state has been applied to realize large crystal grain poly-Si thin films, these films however had random orientations causing a high variation of TFTs' performance.…”

Characterization of Continuous-Wave Laser Crystallized Silicon Thin Films with Hole-Patterns

“…However, after a lot of attempts to improve the TFT's performance including the pressure-induced nucleation (PIN) method, they have had the mobility of below 180 cm 2 V −1 s −1 owing to small silicon crystal grains. [11][12][13] It has been reported that the performance of poly-Si TFTs has been improved with approximately 300 cm 2 V −1 s −1 electron mobility by the sequential lateral solidification (SLS) method. 14 Thermal plasma jet (TPJ) has been applied to realize LTPS-TFTs with electron mobility of 300 cm 2 V −1 s −1 .…”

Poly-Si Thin-Film Transistors with N-Type Line-Array Doping Channels Fabricated by Nanoimprint Lithography

“…Polycrystalline-silicon thin-film transistors (poly-Si TFTs) are potential devices for various applications, including active-matrix organic light-emitting diodes (AMOLEDs), active-matrix liquid crystal displays (AMLCDs), [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16] nonvolatile memories, [17][18][19] sensors, 20 and three-dimensional (3D) integrated circuits (ICs). [21][22][23][24][25] Poly-Si TFTs with the modified channels, such as the nanowire (NW), [9][10][11][12] multigate, 24 finlike, 15,16 and bridge-grain (BG) TFTs, 13,14 have been proposed to improve electrical performance. In these methods, dense and/or periodic nanoscale patterns must be introduced on the poly-Si TFTs channels.…”

“…The related concept is proposed and studied for the p-type channel poly-Si TFTs. 13,14 However, for the 3D IC applications, [21][22][23][24][25] high-performance CMOS circuits with n-and p-type channel poly-Si TFTs are required. Moreover, the n-channel poly-Si TFT circuit that can reduce the supply voltage of drivers, is an alternative candidate for the low-power and high performance pixel circuits of AMOLED displays.…”