Foundry manufacturing of tight-confinement, dispersion-engineered, ultralow-loss silicon nitride photonic integrated circuits

Abstract

The foundry development of integrated photonics has revolutionized today’s optical interconnect and datacenters. Over the last decade, we have witnessed the rising of silicon nitride (Si3N4) integrated photonics, which is currently transferring from laboratory research to foundry manufacturing. The development and transition are triggered by the ultimate need for low optical loss offered by Si3N4, which is beyond the reach of silicon and III-V semiconductors. Combined with modest Kerr nonlinearity, tight optical confinement, and dispersion engineering, Si3N4 has today become the leading platform for linear and Kerr nonlinear photonics, and it has enabled chip-scale lasers featuring ultralow noise on par with table-top fiber lasers. However, so far all the reported fabrication processes of tight-confinement, dispersion-engineered Si3N4 photonic integrated circuits (PICs) with optical loss down to few dB/m have only been developed on 4-inch (100 mm diameter) or smaller wafers. Yet, to transfer these processes to established CMOS foundries that typically operate 6-inch or even larger wafers, challenges remain. In this work, we demonstrate the first foundry-standard fabrication process of Si3N4 PICs with only 2.6 dB/m loss, thickness above 800 nm, and near 100% fabrication yield on 6-inch (150 mm diameter) wafers. Such thick and ultralow-loss Si3N4 PIC enables low-threshold generation of soliton frequency combs. Merging with advanced heterogeneous integration, active ultralow-loss Si3N4 integrated photonics could pave an avenue to addressing future demands in our increasingly information-driven society.

Compact microring resonator based on ultralow-loss multimode silicon nitride waveguide

“…However, the key to achieving low propagation loss all include introducing complex fabrication processes solely to minimize the scattering points at the waveguide interfaces, such as reflowing resist masks, 11,25,27 multipass lithography, 19,28 and optimizing the etch recipe. 10,19 These special fabrication techniques are nonstandard and incompatible with those standard processes in foundries. Notably, all of the reported high-Q Si 3 N 4 MRRs are fabricated in laboratories, not for the MPW.…”

“…19,28 A propagation loss as low as 2.6 dB∕m or even lower is also achieved by introducing extra fabrication processes, such as multipass lithography, optimized etch recipe, surface smoothing technique, or thermal anneal. 10,19,28,29 However, one should note that these special fabrication techniques are not standard and are usually incompatible for foundries. Moreover, these complex fabrication approaches are not available generally for different material platforms.…”

“…[6][7][8][9] The 5 eV bandgap of Si 3 N 4 makes it transparent from ultraviolet to mid-infrared, and immune to two-photon absorption in the telecommunication band, which means it has very low propagation loss. 10 Combining with its high Kerr nonlinearity and weak Brillouin scattering, Si 3 N 4 has become the material of choice, particularly for Kerr nonlinear photonics. 11 Because of these advantages, the Si 3 N 4 waveguides have been proposed to be integrated with other active and passive optical components [12][13][14][15][16][17] to boost the performance of the device.…”

“…For example, if the chemical mechanical planarization polishing rates for the waveguide material and cladding are different, the dishing effect may occur, which may lead to significant structure distortion and top surface roughness. 10 Alternatively, Si 3 N 4 waveguides can be fabricated using traditional subtractive processing methods, where the Si 3 N 4 film is lithographically patterned. 19,28 A propagation loss as low as 2.6 dB∕m or even lower is also achieved by introducing extra fabrication processes, such as multipass lithography, optimized etch recipe, surface smoothing technique, or thermal anneal.…”

Silicon photonics enabled universal cross-scale tensor processing on chip

“…However, they still fall short of meeting the ever-increasing computational demands of arti cial intelligence 29 . To address this issue, two prominent strategies have been emerged, which are improving device performance 11,13,14,17,30 and expanding the number of computational units (i.e., neurons) [31][32][33][34] . Speci cally, speed improvements of devices are limited by the material properties of silicon and can only be optimized via complex heterogeneous integration design or electronic doping, while scaling up computations is hindered by the lack of on-chip optical ampli ers in silicon photonic platforms, resulting in substantial power loss within large-scale integrated chip 35 .…”