FPGA acceleration of a quantum Monte Carlo application

Gothandaraman, Akila; Peterson, Gregory D.; Warren, Gregory L.; Hinde, Robert J.; Harrison, Robert J.

doi:10.1016/j.parco.2008.01.009

Cited by 32 publications

(19 citation statements)

References 10 publications

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“…This equation then gives the one-dimensional time-independent Schrödinger equation for a chargeless particle of mass, m, moving in a potential, V (x). The analogous threedimensional time-independent equation is given by (3). Solving this equation is trivial for small systems, but as the dimensions of the system increase, it is impractical to solve the equation analytically.…”

Section: Algorithmmentioning

confidence: 99%

“…We use a flavor of QMC called the Variational Monte Carlo (VMC) algorithm [2,3]. In Step 1 of the algorithm, …”

Section: Algorithmmentioning

confidence: 99%

“…From our initial experiments varying the order of interpolation, we infer that quadratic interpolation with coefficients (a, b, c) guarantees the required accuracy with modest use of BRAM resources. The potential energy and wave function are divided into two regions, region I and 4 VLSI Design region II with each region approximated using a unique set of interpolation coefficients [3]. The lookup tables for each function store 256 (a1, b1, c1) 52-bit coefficients for region I and 1344 (a2, b2, c2) 52-bit coefficients for region II.…”

Section: Lookup Tablesmentioning

confidence: 99%

“…We propose a reconfigurable hardware architecture using Field-Programmable Gate Arrays (FPGAs) to implement the kernels of our application. In [3,4], we presented our ongoing research and our hardware accelerated framework where we achieve promising results when the kernels of the application are ported to the Cray XD1 reconfigurable supercomputing platform [5]. Here, we focus on the architectural details, our design goals, and choices while designing the pipelined architecture to calculate the potential energy and wave function of atomic clusters.…”

Section: Introductionmentioning

confidence: 99%

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A Pipelined and Parallel Architecture for Quantum Monte Carlo Simulations on FPGAs

et al. 2010

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Recent advances in Field-Programmable Gate Array (FPGA) technology make reconfigurable computing using FPGAs an attractive platform for accelerating scientific applications. We develop a deeply pipelined and parallel architecture for Quantum Monte Carlo simulations using FPGAs. Quantum Monte Carlo simulations enable us to obtain the structural and energetic properties of atomic clusters. We experiment with different pipeline structures for each component of the design and develop a deeply pipelined architecture that provides the best performance in terms of achievable clock rate, while at the same time has a modest use of the FPGA resources. We discuss the details of the pipelined and generic architecture that is used to obtain the potential energy and wave function of a cluster of atoms.

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Section: Algorithmmentioning

confidence: 99%

“…We use a flavor of QMC called the Variational Monte Carlo (VMC) algorithm [2,3]. In Step 1 of the algorithm, …”

Section: Algorithmmentioning

confidence: 99%

Section: Lookup Tablesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Pipelined and Parallel Architecture for Quantum Monte Carlo Simulations on FPGAs

et al. 2010

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“…Enhancing the cluster parallelism by hardware acceleration is of increasing interest to the realm of High Performance Computing (HPC). In the case of Monte Carlo methods, the most exploited stochastic technique in numerous scientific areas, recent works have shown that hardware acceleration using Field Programmable Gate Arrays (FPGA) can improve speed performance by several orders [1], [2], [3]. Monte Carlo methods are inherently parallel and make extensive use of non-uniform distributions; thus a particular attention has been recently given to hardware-based non-uniform random number generators, the targeted distributions being the normal, the log-normal, the Weibull, the Rayleigh and the exponential distributions [4], [5], [6].…”

Section: Introductionmentioning

confidence: 99%

A new hardware architecture for sampling the exponential distribution

Ould-Bachir

Sawan

Brault

2008

2008 Canadian Conference on Electrical and Computer Engineering

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Hardware acceleration in high performance computing context is of growing interest, particularly in the field of Monte Carlo methods where the resort to FPGA technology enhances execution speed by several orders. For this purpose, a particular attention has been given lately to hardware-based non-uniform random variate generators. In this paper we present both a hardware-dedicated decision tree technique for the generation of exponential variates and a derived architecture implemented in FPGA. The proposed design passes the χ 2 test with a p-value of 0.5499 and ensures absence of serial correlation. The exponential random number generator reaches 375 MHz on a Xilinx Virtex II Pro FPGA and occupies about 3 % of the available space.

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Special‐Purpose Hardware for Computational Biology

Srinivasan

2012

Embedded Systems

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FPGA acceleration of a quantum Monte Carlo application

Cited by 32 publications

References 10 publications

A Pipelined and Parallel Architecture for Quantum Monte Carlo Simulations on FPGAs

A Pipelined and Parallel Architecture for Quantum Monte Carlo Simulations on FPGAs

A new hardware architecture for sampling the exponential distribution

Special‐Purpose Hardware for Computational Biology

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