FPGA accelerator for real-time SIFT matching with RANSAC support

Vourvoulakis, John; Kalomiros, John; Lygouras, John N.

doi:10.1016/j.micpro.2016.11.011

Cited by 24 publications

(10 citation statements)

References 20 publications

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“…There are CPU, 11,12 GPU 13,14 and FPGA implementations. [15][16][17][18][19][20] The OpenCV SIFT library 11 and the OpenSIFT 12 are popular frameworks for SIFT keypoint extraction and descriptor computation in CPUs. This is partially due to their flexibility as the input image resolution can be modified easily.…”

Section: Related Workmentioning

confidence: 99%

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Implementation of Scale Invariant Feature Transform detector on FPGA for low‐power wearable devices for prostheses control

Fejér

Nagy

Benois‐Pineau

et al. 2021

Circuit Theory & Apps

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In this paper we describe an FPGA implementation of the Scale Invariant Feature Transform (SIFT) algorithm. The FPGA is required as its a lightweight device which makes it ideal for vision-guided hybrid neuro-prostheses utilised for upper limbs replacement. SIFT point detection is needed for computation of coordinates of the object-to-grasp in a wearable multi-camera system. A modified SIFT algorithm is proposed and an implementation of it into C/C++ language on Xilinx ZCU102 FPGA board. The proposed hybrid hardware/ software solution is compared to other hardware or hybrid implementations of the SIFT algorithm and with the baseline software detector OpenSIFT. The algorithm optimised for FPGA gives an average precision of 0.84 and the average recall of 0.94 in SIFT-point detection compared to the baseline.The proposed solution has lower dissipated power than other solutions like CPU or GPU, and it has better computational speed. This solution allows for processing medium-sized images in real-time with low power consumption.

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Section: Related Workmentioning

confidence: 99%

“…Vourvoulakis et al 17,18 implemented an FPGA accelerated SIFT matching with RANSAC support. The architecture includes one octave and four scales.…”

Section: Related Workmentioning

confidence: 99%

Implementation of Scale Invariant Feature Transform detector on FPGA for low‐power wearable devices for prostheses control

Fejér

Nagy

Benois‐Pineau

et al. 2021

Circuit Theory & Apps

View full text Add to dashboard Cite

show abstract

“…The quantities of LEs in [14] and [28] are close to the proposed stereo vision system, but the resulting frame rates are only about 40 fps. The stereo vision system proposed by [29] uses many hardware resources, but the resulting frame rate is only half of the proposed approach. In summary, the proposed double E-SIFT with FAP feature matching has a satisfactory frame rate with an acceptable hardware cost.…”

Section: Performance Of Proposed E-siftmentioning

confidence: 99%

FPGA Design of Enhanced Scale-Invariant Feature Transform with Finite-Area Parallel Feature Matching for Stereo Vision

et al. 2021

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In this paper, we propose an FPGA-based enhanced-SIFT with feature matching for stereo vision. Gaussian blur and difference of Gaussian pyramids are realized in parallel to accelerate the processing time required for multiple convolutions. As for the feature descriptor, a simple triangular identification approach with a look-up table is proposed to efficiently determine the direction and gradient of the feature points. Thus, the dimension of the feature descriptor in this paper is reduced by half compared to conventional approaches. As far as feature detection is concerned, the condition for high-contrast detection is simplified by moderately changing a threshold value, which also benefits the reduction of the resulting hardware in realization. The proposed enhanced-SIFT not only accelerates the operational speed but also reduces the hardware cost. The experiment results show that the proposed enhanced-SIFT reaches a frame rate of 205 fps for 640 × 480 images. Integrated with two enhanced-SIFT, a finite-area parallel checking is also proposed without the aid of external memory to improve the efficiency of feature matching. The resulting frame rate by the proposed stereo vision matching can be as high as 181 fps with good matching accuracy as demonstrated in the experimental results.

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“…Finally, the previous features (stored in a 2D Shift Register) and the current features were matched using the hamming distances as discrimination metric. In 2017, Vourvoulakis [23] presented an FPGA-SIFT architecture for feature matching. In order to achieve high hardware parallelism, procedures of SIFT detection and description were reformulated.…”

Section: Related Workmentioning

confidence: 99%

“…In most of cases, previous FPGA-based feature matching formulations, [24,17,8,15,5,26,25,16,23] provide relatively good performance under real world scenarios. Unfortunately, in several applications and in particular smart cameras applications, these algorithms are not compliant due to their relatively high hardware requirements and their algorithmic formulation.…”

Section: Related Workmentioning

confidence: 99%

Dense Feature Matching Core for FPGA-based Smart Cameras

Aguilar-González

Arias-Estrada

Berry

2017

Proceedings of the 11th International Conference on Distributed Smart Cameras

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International audienceSmart cameras are image/video acquisition devices that integrate image processing algorithms close to the image sensor, so they can deliver high-level information to a host computer or high-level decision process. In this context, a central issue is the implementation of complex and computationally intensive computer vision algorithms inside the camera fabric. For low-level processing, FPGA devices are excellent candidates because they support data paral-lelism with high data throughput. One computer vision algorithm highly promising for FPGA-based smart cameras is feature matching. Unfortunately, most previous feature matching formulations have inefficient FPGA implementations or deliver relatively poor information about the observed scene. In this work, we introduce a new feature-matching algorithm that aims for dense feature matching and at the same time straightforward FPGA implementation. We propose a new mathematical formulation that addressed the feature matching task as a feature tracking problem. We demonstrate that our algorithmic formulation delivers robust feature matching with low mathematical complexity and obtains accuracy superior to previous algorithmic formulations. An FPGA architecture is lay down and, hardware acceleration strategies are discussed. Finally , we applied our feature matching algorithm in a monocular-SLAM system. We show that our algorithmic formulation provides promising results under real world applications

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FPGA accelerator for real-time SIFT matching with RANSAC support

Cited by 24 publications

References 20 publications

Implementation of Scale Invariant Feature Transform detector on FPGA for low‐power wearable devices for prostheses control

Implementation of Scale Invariant Feature Transform detector on FPGA for low‐power wearable devices for prostheses control

FPGA Design of Enhanced Scale-Invariant Feature Transform with Finite-Area Parallel Feature Matching for Stereo Vision

Dense Feature Matching Core for FPGA-based Smart Cameras

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