FPGA &amp; VPU Co-Processing in Space Applications: Development and Testing with DSP/AI Benchmarks

Leon, Vasileios; Bezaitis, Charalampos; Lentaris, George; Soudris, Dimitrios; Reisis, D.; Papatheofanous, Elissaios Alexios; Kyriakos, Angelos; Dunne, Aubrey; Samuelsson, Arne; Steenari, David

doi:10.1109/icecs53924.2021.9665462

Cited by 11 publications

(3 citation statements)

References 12 publications

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“…101,102 The Phi-Sat 1 system consists of eyes of things (EoT) system with the Myriad 2 vision processing unit along with a HyperScout 2, which is a miniaturized spectral camera, which can be used to capture data in the near-infrared and thermal infrared regions. The Myriad 2 vision processing unit is an SoC with integrated DRAM RISC-V processors, streaming hybrid architecture vector engines, and can compute with a steady voltage supply of 2 V. [101][102][103][104]106 The NN on the Phi-SAT-1 was trained using modified data from European Space Agency's Sentinal 2 archive. The modification was done to simulate the behavior of the HyperScout 2 system.…”

Section: Onboard Enabling Technologiesmentioning

confidence: 99%

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Machine Learning and Deep Learning powered satellite communications: Enabling technologies, applications, open challenges, and future research directions

Bhattacharyya

Nambiar

Ojha

et al. 2023

Satell Commun Network

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SummaryThe recent wave of creating an interconnected world through satellites has renewed interest in satellite communications. Private and government‐funded space agencies are making advancements in the creation of satellite constellations, and the introduction of 5G has brought a new focus to a fully connected world. Satellites are the proposed solutions for establishing high throughput and low latency links to remote, hard‐to‐reach areas. This has caused the injection of many satellites in Earth's orbit, which has caused many discrepancies. There is a need to establish highly adaptive and flexible satellite systems to overcome this. Machine Learning (ML) and Deep Learning (DL) have gained much popularity when it comes to communication systems. This review extensively provides insight into ML and DL's utilization in satellite communications. This review covers how satellite communication subsystems and other satellite system applications can be implemented through Artificial Intelligence (AI) and the ongoing open challenges and future directions.

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Section: Onboard Enabling Technologiesmentioning

confidence: 99%

“…They were compared with an ARM chip, a Myriad processor, and a Jetson Nano. The same authors Leon et al 106 proposed FPGA development and testing for digital signal processing and AI benchmarking. Their accelerator consists of a vision processing unit, hardware filters, and AI engines.…”

Section: Enabling Technologiesmentioning

confidence: 99%

Machine Learning and Deep Learning powered satellite communications: Enabling technologies, applications, open challenges, and future research directions

Bhattacharyya

Nambiar

Ojha

et al. 2023

Satell Commun Network

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“…Furthermore, we do not focus on CubeSat missions because these missions often use simpler platforms based only on micro-controllers, such as Arm cortex-M or TI MSP430 [1]. Many launched missions have used LEON processors and an RTAX Field-Programmable Gate Array (FPGA) [2]. However, the Arm Cortex series is a newly emerging CPU option.…”

Section: Introductionmentioning

confidence: 99%

On-board Payload Data Processing Combined with the Roofline Model for Hardware/Software Design

Lee,

Casseau,

Kritikakou

et al. 2024

2024 IEEE Aerospace Conference

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High-performance on-board payload data processing has become more interesting with the development of radiationhardened multiprocessor System-on-chip (MPSoC). As recent space-qualified MPSoCs include Arm Central Processing Units (CPUs) and Field Programmable Gate Arrays (FPGAs), an efficient design method is required to deal with complex heterogeneous embedded systems. Both data bit-width (data accuracy) and processing performance are important in astronomy, thus the design methodology should concern application-specific Multi-Objective Optimization Problems (MOOPs). This paper proposes to combine the roofline performance model with Design Space Exploration (DSE) of hardware/software designs as a methodology. We use High-Level Synthesis (HLS) for FPGA design to configure different hardware architectures based on C/C++ and pragmas. We develop a benchmark for payload data processing on Arm CPUs and embedded FPGA on a heterogeneous MPSoC by adapting open-source libraries for one of the most commonly used algorithms to provide validated libraries to payload teams. The benchmark takes as constraints the SVOM ECLAIRs payload requirements, and as input data the CCSDS test images, executes applications, and verifies output data. We chose an AMD-Xilinx Zynq UltraScale+ evaluation board and the two-Dimensional Fast Fourier Transform (2-D FFT) as a DSE use case. We designed the benchmark on an Arm Cortex-A53 in bare-metal and an embedded FPGA based on Vitis HLS. The results show a customized roofline model with the hardware/software design. The implemented design has 1.6-55 times faster performance compared to the payload execution time requirement. Based on the proposed roofline model and the DSE results, future payload teams can study the trade-off between execution time and area efficiency to select the most suitable implementation.

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Increasing the Fault Tolerance of COTS FPGAs in Space: SEU Mitigation Techniques on MPSoC

Pagonis,

Leon,

Soudris

et al. 2023

Lecture Notes in Computer Science

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FPGA & VPU Co-Processing in Space Applications: Development and Testing with DSP/AI Benchmarks

Cited by 11 publications

References 12 publications

Machine Learning and Deep Learning powered satellite communications: Enabling technologies, applications, open challenges, and future research directions

Machine Learning and Deep Learning powered satellite communications: Enabling technologies, applications, open challenges, and future research directions

On-board Payload Data Processing Combined with the Roofline Model for Hardware/Software Design

Increasing the Fault Tolerance of COTS FPGAs in Space: SEU Mitigation Techniques on MPSoC

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