FPGA and ASIC Implementations of AES

Gaj, Kris; Chodowiec, Paweł

doi:10.1007/978-0-387-71817-0_10

Cited by 51 publications

(32 citation statements)

References 18 publications

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“…Table 3 also shows the variants using Poly. From the results shown in Table 3 we can infer the following: The sequential decryption core in HMCH[BRW] was implemented using the techniques in [8]. In [8] the operations BS and MC are combined in a substitution operation which the authors call as T-boxes.…”

Section: Resultsmentioning

confidence: 99%

“…From the results shown in Table 3 we can infer the following: The sequential decryption core in HMCH[BRW] was implemented using the techniques in [8]. In [8] the operations BS and MC are combined in a substitution operation which the authors call as T-boxes. In our implementation for the decryption core we used inverse T-boxes (iTbox) which combines the operations inverse byte substitution (iBS) and inverse mixcolumn (iMC).…”

Section: Resultsmentioning

confidence: 99%

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Efficient hardware implementations of brw polynomials and tweakable enciphering schemes

Chakraborty

Mancillas-López

Rodríguez-Henríquez

et al. 2013

IEEE Trans. Comput.

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multiplications and log 2 m squarings for BRW hashing, where m is the number of message blocks to be authenticated. In this paper, we develop an efficient pipelined hardware architecture for computing BRW polynomials. The BRW polynomials have a nice recursive structure which is amenable to parallelization. While exploring efficient ways to exploit the inherent parallelism in BRW polynomials we discover some interesting combinatorial structural properties of such polynomials. These are used to design an algorithm to decide the order of the multiplications which minimizes pipeline delays. Using the nice structural properties of the BRW polynomials we present a hardware architecture for efficient computation of BRW polynomials. Finally we provide implementations of tweakable enciphering schemes proposed in Sarkar 2009 which uses BRW polynomials. This leads to the fastest known implementation of disk encryption systems.

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Efficient hardware implementations of brw polynomials and tweakable enciphering schemes

Chakraborty

Mancillas-López

Rodríguez-Henríquez

et al. 2013

IEEE Trans. Comput.

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“…The SubBytes and InvSubBytes steps are often considered as the most critical part of the AES, and several architectures for S RD and S −1 RD have already been described in the open literature (see for instance [12] for a comprehensive bibliography). On Xilinx Virtex-6 FPGAs, the best design strategy consists in implementing the AES S-boxes as 8-input tables [10].…”

Section: Arithmetic and Logic Unitmentioning

confidence: 99%

A low-area unified hardware architecture for the AES and the cryptographic hash function Grøstl

Beuchat

Okamoto

et al. 2017

Journal of Parallel and Distributed Computing

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Abstract-This article describes the design of an 8-bit coprocessor for the AES (encryption, decryption, and key expansion) and the cryptographic hash function Grøstl on several Xilinx FPGAs. Our Arithmetic and Logic Unit performs a single instruction that allows for implementing AES encryption, AES decryption, AES key expansion, and Grøstl at all levels of security. Thanks to a careful organization of AES and Grøstl internal states in the register file, we manage to generate all read and write addresses by means of a modulo-128 counter and a modulo-256 counter. A fully autonomous implementation of Grøstl and AES on a Virtex-6 FPGA requires 169 slices and a single 36k memory block, and achieves a competitive throughput. Assuming that the security guarantees of Grøstl are at least as good as the ones of the other SHA-3 finalists, our results show that Grøstl is the best candidate for low-area cryptographic coprocessors.

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“…is a multiplication modulo the irreducible polynomial m(x)= x 8 +x 4 +x 3 +x+1 [11]. More information about AES algorithm is in [1,10].…”

Section: Columns Functionmentioning

confidence: 99%

Design of a Specific Instructions Set Processor for AES Algorithm

Shahbazi¹,

Eshghi²

2014

IJCA

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In this paper, a new architecture for Advanced Encryption Standard (AES) Algorithm based on Application Specific Instruction set Processors (ASIP) design technique is proposed. The basic configuration is developed in order to reduce the execution clock pulses for the main specific instructions. According to the improvement of the first register configuration, two ASIPs are designed for AES algorithm. The second ASIP is 89% faster and have 22% less gates than the first proposed design.

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FPGA and ASIC Implementations of AES

Cited by 51 publications

References 18 publications

Efficient hardware implementations of brw polynomials and tweakable enciphering schemes

Efficient hardware implementations of brw polynomials and tweakable enciphering schemes

A low-area unified hardware architecture for the AES and the cryptographic hash function Grøstl

Design of a Specific Instructions Set Processor for AES Algorithm

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