FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis

Abstract

We propose strategies to achieve a high-throughput FPGA architecture for quasi-cyclic low-density parity-check codes based on circulant-1 identity matrix construction. By splitting the node processing operation in the min-sum approximation algorithm, we achieve pipelining in the layered decoding schedule without utilizing additional hardware resources. High-level synthesis compilation is used to design and develop the architecture on the FPGA hardware platform. To validate this architecture, an IEEE 802.11n compliant 608 Mb/s decoder is implemented on the Xilinx Kintex-7 FPGA using the LabVIEW FPGA Compiler in the LabVIEW Communication System Design Suite. Architecture scalability was leveraged to accomplish a 2.48 Gb/s decoder on a single Xilinx Kintex-7 FPGA. Further, we present rapidly prototyped experimentation of an IEEE 802.16 compliant hybrid automatic repeat request system based on the efficient decoder architecture developed. In spite of the mixed nature of data processing-digital signal processing and finite-state machines-LabVIEW FPGA Compiler significantly reduced time to explore the system parameter space and to optimize in terms of error performance and resource utilization. A 4x improvement in the system throughput, relative to a CPU-based implementation, was achieved to measure the error-rate performance of the system over large, realistic data sets using accelerated, in-hardware simulation.

FPGA Implementation of 5G NR LDPC Codes

“…As an all-in-one solution for various engineering projects, the software also provides a variety of tools for signal processing, data analysis, and visualization. Overall, LabVIEW is a potent tool that may facilitate and accelerate the design of complicated systems for engineers and scientists [17].…”

FPGA based technical solutions for high throughput data processing and encryption for 5G communication: A review

“…Concerning FPGA employment in coding operations, in [24], the authors proposed quasi-cyclic low-density parity-check (LDPC) codes that rely on a base matrix comprising several sub-matrices, including the cyclically right-shifted identity one and the null one. The Vivado HLS (High-level synthesis) tool has been used to synthesize the proposed coding scheme on the Xilinx Kintex-7 FPGA platform.…”