FPGA based design of area efficient router architecture for Network on Chip (NoC)

Kumar, Mayank; Kumar, K. Seshu; Gupta, Sanjiv Kumar; Kumar, Yogendera

doi:10.1109/ccaa.2016.7813980

Cited by 3 publications

(3 citation statements)

References 15 publications

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“…On implementation, combination of CLOS and circuit switched switch performed better than normal crossbar with a large reduction in area. A new area efficient reconfigurable router architecture for NoCs was introduced in [56]. Design was carried using hardware description language.…”

Section: Areamentioning

confidence: 99%

A Review of Design Approaches for Enhancing the Performance of NoCs at Communication Centric Level

Manzoor

Mir

Hakim

2021

SCPE

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As the trend of technology shrinking continues a vast amount of processors are being incorporated in a limited space. Due to this almost half of the chip area in Multi-Processor Systems-on-Chips (MPSoCs) is under interconnections, which pose a big problem for communication. Network-on-Chips (NoCs) evolved as a significant scalable solution for removing wiring congestion and communication problem in MPSoCs. NoCs provide the advantage of customized architecture, increased scalability and bandwidth. NoC is a structured framework where communication is the prime concern. In this review paper we present an overview of research and design approaches in the communication centric areas of NoCs. Here we have tried to discuss and iterate most of the available work done for communication in 2D NoCs. This paper gives the insight of different attributes and performance parameters of NoCs. Further it gives a detailed description of how topology, flow control and routing mechanisms can affect the qualitative aspects (performance) of NoCs. It then explains how various attributes of routing can help in increasing the efficacy of NoCs. Subsequently a brief review of different simulators used for NoCs is given. All of this is provided based on the survey of academic, theoretical and experimental approaches presented in the past. Finally some suggestions for future work are also given.

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Section: Areamentioning

confidence: 99%

A Review of Design Approaches for Enhancing the Performance of NoCs at Communication Centric Level

Manzoor

Mir

Hakim

2021

SCPE

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“…The work of Aslam et al [7] has concentrated on the development of a routing protocol technique for efficient Network on-chip transmission, in here introduce a Junction-based routing protocol about this protocol it is a suitable technique for log Network on chip platforms. The study of Kumar et al [8] have focused on the design of area-efficient router framework based on FPGA for Network on chip, Once the completing of the design of channels, the crossbar is also designed and after the completing the process of design of crossbar and all four channels both designed are integrated with the making of the framework of a router. The work of Lu et al [9] have concentrated on the problem of delay in packet transmission and cost in routing, for solving this issue presented a Low-Latency NoC Router framework.…”

Section: Related Workmentioning

confidence: 99%

Fpga Implementation of Priority-Arbiter Based Router Design for Noc Systems

Nirmala¹,

Shylaja²

2019

IJARET

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An efficient Priority-Arbiter based Router is designed along with 2X2 and 3X3 mesh topology-based NOC architecture are designed. The Priority-Arbiter based Router design includes Input registers, Priority arbiter, and XY-Routing algorithm. The Priority-Arbiter based Router and NOC 2X2 and 3X3 Router designs are synthesized and implemented using Xilinx ISE Tool and simulated using Modelsim6.5f. The implementation is done by Artix-7 FPGA device, and the physically debugging of the NOC 2X2 Router design is verified using Chipscope pro tool. The performance results are analyzed in terms of the Area (Slices, LUT's), Timing period, and Maximum operating frequency. The comparison of the Priority-Arbiter based Router is made concerning previous similar architecture with improvements.

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“…There are numerous types of interconnections like point-to-point, bus architecture, carbon nanotubes, optical fiber [1] where NoC perform is better to reduce the interconnection issues in future designs. System on chips designed using NoCs are getting popular in these days which provide solutions to the problem related to bus based designs and considered as the future of the application specific integrated circuit (ASIC) design [2]. NoC basically has three building blocks router, links and network adapter (NA) [3].…”

mentioning

confidence: 99%

An efficient FPGA based NoC architecture for data communication

Jamagoud¹,

Bhairannawar²

2018

IJACR

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NoC is a new model in which a single silicon chip is utilized to execute various communication features used in substantial to huge scale integration systems. NoC is another change to the universe of systems and also the other way to deal with disadvantages like wiring delay. There are numerous types of interconnections like point-to-point, bus architecture, carbon nanotubes, optical fiber [1] where NoC perform is better to reduce the interconnection issues in future designs. System on chips designed using NoCs are getting popular in these days which provide solutions to the problem related to bus based designs and considered as the future of the application specific integrated circuit (ASIC) design [2]. NoC basically has three building blocks router, links and network adapter (NA) [3]. NoC approach has numerous benefits over traditional bus method and also provides high throughput as buses are less scalable and limited bandwidth [4].

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FPGA based design of area efficient router architecture for Network on Chip (NoC)

Cited by 3 publications

References 15 publications

A Review of Design Approaches for Enhancing the Performance of NoCs at Communication Centric Level

A Review of Design Approaches for Enhancing the Performance of NoCs at Communication Centric Level

Fpga Implementation of Priority-Arbiter Based Router Design for Noc Systems

An efficient FPGA based NoC architecture for data communication

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