FPGA based design of low power reconfigurable router for Network on Chip (NoC)

Bhanwala, Amit; Kumar, Mayank; Kumar, Yogendera

doi:10.1109/ccaa.2015.7148581

Cited by 13 publications

(5 citation statements)

References 12 publications

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“…If an NoC router has a larger FIFO buffer, the network will have higher throughput [16] and smaller latency as there will be fewer flits stagnant on the network .Since, each communication will have its peculiarities, sizing the FIFO for the worst case communication sce- nario will compromise not only the routing area, but power [17] as well. However, if the router has a small FIFO depth, the latency will be larger and the quality of service (QoS) can be compromised.…”

Section: Reconfigurable Routermentioning

confidence: 99%

Design of Priority Based Reconfigurable Router in Network on Chip

2020

Informacije MIDEM

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Network on Chip (NoC) is an advanced integration design for communication networks while providing a solution to the traditional bus based System on Chip designs (SoC) too. A router is a key component which is considered as the backbone of communication in NoC. The objective of this work is to design a priority based reconfigurable router for NoC. Initially, a 4x4 Baseline router is designed and synthesised and then the channels inside the router are modified to achieve reconfiguration to improve the router's efficiency. In 4x4 Reconfigurable Router the slots are well utilized but prioritization portion is not considered. Routers are associated with switches to take data transfer decisions resulting in high power consumption. In order to overcome this problem, a new priority based reconfigurable router is designed. The design for this router is carried out using Verilog HDL and synthesized and simulated using Xilinx ISE Design Suite 14.3 and ModelSim-Altera 6.5b Software respectively. The corresponding results in terms of power, energy efficiency, area and delay are analysed and the proposed work gives better results than the conventional Baseline Router. Dizajn prioritetno nastavljivega usmerjevalnika v omrežju na čipuIzvleček: Omrežkje na čipu (NoC) je napredna integracija komunikacijskih omrežij z uporabo tradicionalnih sitemov na čipu na osnovi vodil (SoC). Usmerjevalnik predstavlja ključno komponento v komunikaciji preko NoC. Namen dela je razvoj prioritetno nastavljivega usmerjevalnika za NoC. V osnovi je uporabljen 4x4 usmerjevalnik, v kateremu so, za doseganje učinkovitosti, kanali naknadno razširjeni.Reže v nastavljivem usmerjevalniku so dobro uporabljene, vendar ne upoštevajo prioritet. Usmerjevalniki so povezani s stikali za prenos podatkov, ki imajo visoko porabo. Nastavljivi usmrjevalniku rešujejo problem visoke porabe. Dizajn usmerjevalnika je realiziran v Verilog HDL okolju in simuliran z Xilinx ISE Design Suite 14.3 in ModelSim-Altera 5.5b programsko opremo. Rezultati izkazujejo boljšo učinkovitost, nižjo porabo in zakasnitev predlaganega usmerjevalnika.

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Section: Reconfigurable Routermentioning

confidence: 99%

Design of Priority Based Reconfigurable Router in Network on Chip

2020

Informacije MIDEM

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“…The study of Bhanwala et al [1] has focused on the design of reconfigurable Network on chip (NOC) application, based on Field propagation array (FPGA). The design of this complete application is done by the using of Verilog hardware description language.…”

Section: Related Workmentioning

confidence: 99%

Fpga Implementation of Priority-Arbiter Based Router Design for Noc Systems

Nirmala¹,

Shylaja²

2019

IJARET

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An efficient Priority-Arbiter based Router is designed along with 2X2 and 3X3 mesh topology-based NOC architecture are designed. The Priority-Arbiter based Router design includes Input registers, Priority arbiter, and XY-Routing algorithm. The Priority-Arbiter based Router and NOC 2X2 and 3X3 Router designs are synthesized and implemented using Xilinx ISE Tool and simulated using Modelsim6.5f. The implementation is done by Artix-7 FPGA device, and the physically debugging of the NOC 2X2 Router design is verified using Chipscope pro tool. The performance results are analyzed in terms of the Area (Slices, LUT's), Timing period, and Maximum operating frequency. The comparison of the Priority-Arbiter based Router is made concerning previous similar architecture with improvements.

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“…The existing method of router architecture proposed by Bhanawala et al [21] is shown in below figure 1. Here to select the various inputs bit for the desired output the multiplexer will use the addressing bits, which first select a data of input and forward it the multiplexer output.…”

Section: Conventional Noc Architecturementioning

confidence: 99%

Design of Conventional and Modified Router Design for NOC and its FPGA Implementation

Manjunatha¹

2018

CAE

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FPGA Based Systems are helpful improves the performance metrics with high throughput for SOC and NOC Based designs. NOC is an integration of complex-network system into singledevice or a chip. This reduces the manufacturing cost of SOC, increases the performance and reduces the time-consumption. In this paper, two different types of NOC Designs are synthesized and implemented. Firstly, Conventional NOC 2X2 Router includes the 5-channels namely, local, east, north, south and north. Each channel is having 2 Multiplexors along with cross bar switch. Secondly, Proposed NOC 2X2 Router includes 4 Nodes and each Node is having the priority encoder, Random arbiter and router design using XY Algorithms. The proposed designs executing in Xilinx 14.7 and simulated using Modelsim. The outcome of executed scheme gives detailed results with their input and output. The system design is synthesized in Xilinx 14.7 ISE using Verilog and simulated in Modelsim 6.3f and these implemented on FPGA board of version Artix 7. The performance analysis of Proposed NOC 2X2 Router over Conventional NOC 2X2 Router is improves the area overhead and it is tabulated.

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FPGA based design of low power reconfigurable router for Network on Chip (NoC)

Cited by 13 publications

References 12 publications

Design of Priority Based Reconfigurable Router in Network on Chip

Design of Priority Based Reconfigurable Router in Network on Chip

Fpga Implementation of Priority-Arbiter Based Router Design for Noc Systems

Design of Conventional and Modified Router Design for NOC and its FPGA Implementation

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