FPGA-based hardware acceleration for Boolean satisfiability

Abstract

We present an FPGA-based hardware solution to the Boolean satisfiability (SAT) problem, with the main goals of scalability and speedup. In our approach the traversal of the implication graph as well as conflict clause generation are performed in hardware, in parallel. The experimental results and their analysis, along with the performance models are discussed. We show that an order of magnitude improvement in runtime can be obtained over MiniSAT (the best-in-class software based approach) by using a Virtex-4 (XC4VFX140) FPGA device. The resulting system can handle instances with as many as 10K variables and 280K clauses.

A survey of SAT solver

“…There are also designs [56], [57], [58]that implement complete SAT solver algorithms in FPGA. such as Gulati [58].…”

“…For example, the BCP Accelerator [43], which handles a relatively large scale, can accommodate 64K variables and 64K clauses of length 9. The solver [58] can hold 10K variables and 280K fixed-length clauses. The actual scale, however, of the SAT problem in practical applications goes far beyond these limits.…”

“…A number of approaches have been proposed to improve hardware-based solutions such as using larger FPGAs [49] or multiple FPGAs [59][55], splitting problems into smaller subproblems [50], on-demand loading [58], a combination of hardware and software, or solving small subproblems with hardware [56].…”

SatIn: Hardware for Boolean Satisfiability Inference

“…Gulati et al designed a SAT accelerator that sought to perform the entire SAT solving process in hardware [24]. While their algorithm is able to perform the decisions on the accelerator (relying on the CPU to load in new sub-problems as existing ones are satisfied), they do not allow the same intelligent heuristics to be used as a software solver, and do not allow for clause learning.…”