FPGA-based implementation of Horner's rule on a high performance heterogeneous computer

Abstract

Codes that have large/irregular-stride (L/I) memory access patterns often perform poorly on mainstream clusters because of the general purpose processor (GPP) memory hierarchy. In the event of erratic access of data, the cache suffers misses and causes inadequate performance of the kernel. High performance heterogeneous computers (HPHCs) are parallel computing clusters that contain multiple and different processing units such as GPPs, field programmable gate arrays (FPGAs), graphics processing units, etc., connected via a high-speed network. In this research, 64bit floating-point MPI codes are used to illustrate the runtime performance impact of L/I memory accesses in both software-only and FPGA-augmented codes and to assess the benefits of mapping L/I-type codes onto HPHC clusters. The experiments documented herein reveal that large-stride software-only codes experience unfavorable performance. On the contrary, large-stride FPGA-augmented codes do not endure such disparaging performance because FPGAs are not impacted by stride. For experiments with large data sizes, the unit-stride FPGA-augmented code ran over two times slower than software except for when there was substantial data reuse. On the other hand, the large-stride FPGA-augmented code ran faster than software for all the larger data sizes.

Mapping Floating-Point Kernels onto High Performance Reconfigurable Computers

“…Direct memory access (DMA) is used to move data between the Xeon memory and MAP memory. In addition, the MAP processor has a streaming DMA capability, and an inter/intra-FPGA streaming capability that allows overlapping communication and computation [19], [20], [21], [22], [23], [24], [25].…”