FPGA Based Real-Time Emulation System for Power Electronics Converters

Marguč, Jaka; Truntič, Mitja; Rodič, M.; Milanovič, M.

doi:10.3390/en12060969

Cited by 5 publications

(4 citation statements)

References 24 publications

(44 reference statements)

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“…In Figure 6c, the average THD of three-phase reference current is 1.30%, and average THD of three-phase load current of six-switch and four-switch motor emulator are about 1.7% and 1.80%, respectively. From Table 3, comparing to a traditional six-switch motor emulator, although the average switch power loss has increased, the sum of switch power loss decreases 23.81%, according to (18).…”

Section: Motor Emulators With Different Switch Countsmentioning

confidence: 98%

“…Other motor emulators can be found in [16,17], in which the two-level converter is composed of six IGBTs and six antiparallel diodes. In [18], linear inverter structure is applied to reduce the harmonics of load current in the motor emulator, but the cost is double the number of electronic components compare with traditional two-level inverter. The load model of motor emulator proposed in [19] is an inductor-capacitor-inductor (LCL) filter, which improves current ripple induced by high-frequency switch, but increase reactive power consumption.…”

Section: Introductionmentioning

confidence: 99%

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A Power Loss Decrease Method Based on Finite Set Model Predictive Control for a Motor Emulator with Reduced Switch Count

et al. 2019

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This paper presents a power loss decrease method based on finite set model predictive control (FSMPC) with delay compensation for a motor emulator with reduced switch count. Specifically, the topology and mathematical model of the proposed motor emulator with reduced switch count are firstly built. Secondly, in light of given instructions, the normal or fault reference current of the motor emulator is set by a reference current setter. Then delay compensation is applied for the predictive current model to calculate the current residual generated by each switch control signal, and the current tracking performance under actions of two adjacent switch control signals is evaluated for each sector. Finally, a switch power loss objective function is defined, then the two adjacent switch control signals that generate the lowest switch power loss are selected for the next second instant, which minimizes the power loss of the motor emulator with ensuring satisfied current tracking performance. Simulation and experimental results show the feasibility and effectiveness of the proposed method.

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Section: Motor Emulators With Different Switch Countsmentioning

confidence: 98%

Section: Introductionmentioning

confidence: 99%

A Power Loss Decrease Method Based on Finite Set Model Predictive Control for a Motor Emulator with Reduced Switch Count

et al. 2019

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“…There comes an alternative strategy into mind that combines both programmability and high-speed computation: hardware-based co-emulation. Furthermore, real-time power system simulation has already been extensively carried on FPGA [12]- [14] and communication network functions such as Ethernet, TCP/IP are also available as vendor specific IP cores or soft-codes built on FPGA. The multiprocessor system-on-chip (MPSoC) [21] integrates the FPGA based programmable hardware logic and the ARM based multi-core processor systems within one platform, which enable complex embedded applications to be developed.…”

Section: A Motivationmentioning

confidence: 99%

RTCE: Real-Time Co-Emulation Framework for EMT-Based Power System and Communication Network on FPGA-MPSoC Hardware Architecture

Duan

Huang

Dinavahi

2021

IEEE Trans. Smart Grid

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With the expansion of smart grid infrastructure world-wide, modeling the interaction between power systems and communication networks becomes paramount and has created a new challenge of co-simulating the two domains before commissioning. Existing co-simulation methods mostly concentrate on the off-line software-level interface design to synchronize messages between the simulators of both domains. Instead of simulating in software with a large latency, this article proposes a novel real-time co-emulation (RTCE) framework on FPGA-MPSoC based hardware architecture for a more practical emulation of real-world cyber-physical systems. The discrete-time based power system electromagnetic transient (EMT) emulation is executed in programmable hardware units so that the transient-level behaviour can be captured in real-time, while the discrete-event based communication network emulation is modeled in abstraction-level or directly executed on the hardware PHY and network ports of the FPGA-MPSoC platform, which can perform the communication networking in real-time. The data exchange between two domains is handled within each platform with an extremely low latency, which is sufficiently fast for real-time interaction; and the multi-board scheme is deployed to practically emulate the communication between different power system areas. The hardware resource cost and emulation latency for the test system and case studies are evaluated to demonstrate the validity and effectiveness of the proposed RTCE framework.

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“…An FPGA is composed of a matrix of programmable logic blocks. Its main advantage relies on high performance, flexibility and the possibility of multiple reconfiguration of the device [32][33][34][35][36]. Moreover, due to their architecture, FPGAs are parallel by nature [14,37].…”

Section: Introductionmentioning

confidence: 99%

Design of Petri Net-Based Cyber-Physical Systems Oriented on the Implementation in Field Programmable Gate Arrays

Wiśniewski

2021

Energies

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Two design flows of the Petri net-based cyber-physical systems oriented towards implementation in an FPGA are presented in the paper. The first method is based on the behavioural description of the system. The control part of the cyber-physical system is specified by an interpreted Petri net, and is described directly in the synthesisable Verilog hardware language for further implementation in the programmable device. The second technique involves splitting the design into sequential modules. In particular, adequate decomposition and synchronisation algorithms are proposed. The resulting modules are further modelled within the Verilog language as the composition of sequential automata. The presented design flows are supported by theoretical background, and templates of Verilog codes. The proposed techniques are illustrated by a real-life example of a multi-robot cyber-physical system, where each step of the proposed flows is explained in detail, including modelling, description of the system in the Verilog language, and final implementation within the FPGA device. The results obtained during the verification and validation confirm the proper functionality of the system designed by both design flows.

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FPGA Based Real-Time Emulation System for Power Electronics Converters

Cited by 5 publications

References 24 publications

A Power Loss Decrease Method Based on Finite Set Model Predictive Control for a Motor Emulator with Reduced Switch Count

A Power Loss Decrease Method Based on Finite Set Model Predictive Control for a Motor Emulator with Reduced Switch Count

RTCE: Real-Time Co-Emulation Framework for EMT-Based Power System and Communication Network on FPGA-MPSoC Hardware Architecture

Design of Petri Net-Based Cyber-Physical Systems Oriented on the Implementation in Field Programmable Gate Arrays

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