FPGA‐based real‐time implementation for direction‐of‐arrival estimation

Alhamed, Abdulrahman; Tayem, Nizar; Alshawi, Tariq; Alshebeili, Saleh A.; Alsuwailem, Abdullah; Hussain, Ahmed

doi:10.1049/joe.2017.0165

Cited by 11 publications

(10 citation statements)

References 15 publications

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“…The proposed DOA estimation algorithms have superior performance characteristics compared to QR-based methods. The proposed methods also compare favorably with similar FPGA-based implementations of DOA estimation algorithms reported in the literature [12]- [16].…”

Section: Introductionmentioning

confidence: 93%

“…Performance comparison of the proposed LDL and Cholesky-based FPGA implementation of DOA estimation with similar implementations reported in the literature [12]- [16] is presented in Table 5. It can be deduced from the table that the proposed methods are superior to the implementations in [13]- [16] in terms of computation time. The implementation in [13] scores over the proposed methods in terms of resource consumption but it is 15 times slower with computation time of 46 µs.…”

Section: Performance Comparisonmentioning

confidence: 99%

“…The Bartlett DOA estimator in [12] is shown to be an efficient implementation in terms of computation time. FPGA real-time implementation based on QR and LU decompositions have been reported in [16] and [17], respectively. These methods [16], [17] have been shown to be superior in performance (in terms of estimation accuracy, processing time, and resources utilization) to those of MUSIC and ESPRIT-based algorithms reported in the literature.…”

Section: Introductionmentioning

confidence: 99%

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FPGA-Based Hardware Implementation of Computationally Efficient Multi-Source DOA Estimation Algorithms

Hussain¹,

Tayem²,

Soliman³

et al. 2019

IEEE Access

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Hardware implementation of the proposed direction of arrival (DOA) estimation algorithms based on Cholesky and LDL decomposition is presented in this paper. The proposed algorithms are implemented for execution on a field programmable gate array (FPGA) as well as a PC (running LabVIEW) for the multiple non-coherent sources located in the far-field region of a uniform linear array (ULA). Prototype testbeds built using the national instruments (NI) universal software radio peripheral (USRP) software defined radio (SDR) platform and Xilinx Virtex-5 FPGA are originally constructed for the experimental validation of the proposed algorithms. The results from LabVIEW simulations and real-time hardware experiments demonstrate the effectiveness of the proposed algorithms. Specifically, the implementation of the proposed algorithms on a Xilinx Virtex-5 FPGA using the LabVIEW software clarifies their efficiency in terms of computation time and resource utilization, which make them suitable for the real-time practical applications. Moreover, the performance comparison with the QR decomposition-based DOA algorithms as well as similar FPGA-based implementations reported in the literature is conducted in terms of the estimation accuracy, computation speed, and FPGA resources consumed.

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Section: Introductionmentioning

confidence: 93%

Section: Performance Comparisonmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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FPGA-Based Hardware Implementation of Computationally Efficient Multi-Source DOA Estimation Algorithms

Hussain¹,

Tayem²,

Soliman³

et al. 2019

IEEE Access

Self Cite

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“…The denominator in equation (19) shows the inner product of the signal vector a(θ), noise matrix E n , their Hermitian matrices a H (θ) and E H n . When a(θ) is orthogonal with each column of E n , the value of this denominator is zero, but because of the existence of the noise, it actually has some minimum value.…”

Section: Spectral Peak Searchmentioning

confidence: 99%

Towards Low Latency and Resource-Efficient FPGA Implementations of the MUSIC Algorithm for Direction of Arrival Estimation

Butt

Khan

Ullah

et al. 2021

IEEE Trans. Circuits Syst. I

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The estimation of the Direction of Arrival (DoA) is one of the most critical parameters for target recognition, identification and classification. MUltiple SIgnal Classification (MUSIC) is a powerful technique for DoA estimation. The algorithm requires complex mathematical operations like the computation of the covariance matrix for the input signals, eigenvalue decomposition and signal peak search. All these signal processing operations make real-time and resource-efficient implementation of the MUSIC algorithm on Field Programmable Gate Arrays (FPGAs) a challenge.In this paper, a novel design approach is proposed for the FPGAimplementation of the MUSIC algorithm. This approach enables a significant reduction in both FPGA resources and latency. In more detail, the proposed design enables the estimation of DoA in real-time scenarios in 2µsec with 30% to 50% fewer resources as compared to existing techniques.

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“…Various studies have been conducted with regard to the real-time implementation of the ESPRIT. Alhamed performed EVD operations using QR decomposition methods for implementing an ESPRIT processor with low complexity on an FPGA for the purpose of real-time processing [18]. In addition, Hussain designed the ESPRIT processor using LU decomposition to lower the hardware complexity rather than the frequently used QR decomposition method [19].…”

Section: Introductionmentioning

confidence: 99%

Scalable ESPRIT Processor for Direction-of-Arrival Estimation of Frequency Modulated Continuous Wave Radar

et al. 2021

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The estimation of signal parameters via rotational invariance techniques (ESPRIT) is an algorithm that uses the shift-invariant properties of the array antenna to estimate the direction-of-arrival (DOA) of signals received in the array antenna. Since the ESPRIT algorithm requires high-complexity operations such as covariance matrix and eigenvalue decomposition, a hardware processor must be implemented such that the DOA is estimated in real time. Additionally, the ESPRIT processor should support a scalable number of antenna configuration for DOA estimation in various applications because the performance of ESPRIT depends on the number of antennas. Therefore, we propose an ESPRIT processor that supports two to eight scalable antenna configuration. In addition, since the proposed ESPRIT processor is based on multiple invariances (MI) algorithm, it can achieve a much better performance than the existing ESPRIT processor. The execution time is reduced by simplifying the Jacobi method, which has the most significant computational complexity for calculating eigenvalue decomposition (EVD) in ESPRIT. Moreover, the ESPRIT processor was designed using hardware description language (HDL), and an FPGA-based verification was performed. The proposed ESPRIT processor was implemented with 10,088 slice registers, 18,207 LUTs, and 80 DSPs, and the slice register, LUT, and DSP were reduced by up to 71.45%, 54.5%, and 68.38%, respectively, compared to the existing structure.

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FPGA‐based real‐time implementation for direction‐of‐arrival estimation

Cited by 11 publications

References 15 publications

FPGA-Based Hardware Implementation of Computationally Efficient Multi-Source DOA Estimation Algorithms

FPGA-Based Hardware Implementation of Computationally Efficient Multi-Source DOA Estimation Algorithms

Towards Low Latency and Resource-Efficient FPGA Implementations of the MUSIC Algorithm for Direction of Arrival Estimation

Scalable ESPRIT Processor for Direction-of-Arrival Estimation of Frequency Modulated Continuous Wave Radar

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