FPGA-based stochastic neural networks-implementation

Genetic algorithm is a soft computing method that works on set of solutions. These solutions are called chromosome and the best one is the absolute solution of the problem. The main problem of this algorithm is that after passing through some generations, it may be produced some chromosomes that had been produced in some generations ago that causes reducing the convergence speed. From another respective, most of the genetic algorithms are implemented in software and less works have been done on hardware implementation. Our work implements genetic algorithm in hardware that doesn't produce chromosome that have been produced in previous generations. In this work, most of genetic operators are implemented without producing iterative chromosomes and genetic diversity is preserved. Genetic diversity causes that not only don't this algorithm converge to local optimum but also reaching to global optimum. Without any doubts, proposed approach is so faster than software implementations. Evaluation results also show the proposed approach is faster than hardware ones.

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“…In this work linear feedback shift register are used. More details about random number generator can be found in [11,12].…”

Section: B Random Number Generatormentioning

confidence: 99%

New Hardware Engine for New Operating Systems

Ahmadi

Kaveh

2013

ILNS

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“…One example where this phenomenon can be observed is the foraging behavior of ant colonies [1,2]. Ant colonies are capable of finding shortest paths between their nest and food sources.…”

Section: Ant Colony Optimizationmentioning

confidence: 99%

Optimized FPGA Routing using Soft Computing

Saveena¹,

Chopra²,

Singh³

2010

IJCA

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FPGAs are used for a wide range of applications, e.g. network communication, video communication and processing and cryptographic applications. It has been shown that FPGAs are suitable for the implementation of soft computing techniques like Neural Networks and Genetic Algorithms. In this work we have shown that Ant Colony Optimizations can also be implemented on FPGAs, leading to significant speedups in runtime compared to implementations in software on sequential machines. This paper presents an ant colony optimization algorithm for geometric FPGA routing for a route based routing constraint model in FPGA design architecture.

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“…Previous work on hardware implementation of stochastic artificial neural networks can be found in [1,4]. In [1], the activation function is implemented using a lookup table.…”

Section: Introductionmentioning

confidence: 99%

Reconfigurable hardware for neural networks: binary versus stochastic

Nedjah

Mourelle

2007

Neural Comput & Applic

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This paper is focused on hardware implementation of neural networks. We propose a reconfigurable, low-cost and readily available hardware architecture for an artificial neuron. For this purpose, we use field-programmable gate arrays i.e. FPGAs. As the state-of-the-art FPGAs still lack the gate density necessary to the implementation of large neural networks of thousands of neurons, we use a stochastic process to implement efficiently the computation performed by a neuron. This paper describes and compares the characteristics of two architectures designed to implement feed-forward fully connected artificial neural networks: the first FPGA prototype is based on traditional adders and multipliers of binary inputs while the second takes advantage of stochastic representation of the inputs. The paper compares both prototypes using the time · area classic factor.

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FPGA-based stochastic neural networks-implementation

Cited by 81 publications

References 4 publications

New Hardware Engine for New Operating Systems

New Hardware Engine for New Operating Systems

Optimized FPGA Routing using Soft Computing

Reconfigurable hardware for neural networks: binary versus stochastic

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