Reconfigurable Field-Programmable Gate Arrays (FPGAs) provide an effective programmable resource for implementing hardware-based Artificial Neural Networks (ANNs). They are low cost, readily available and reconfigurable -all important advantages for A N N applications. However, FPGAs lack the circuit density necessary to implement large parallel A N N s with many thousands of synapses. This paper presents an architecture that makes it feasible to implement l a q e ANNs with FPGAs. The architecture combines stochastic computation techniques with a novel lookup-table-based architecture that fully exploits the lookup-table structure of many FPGAs. This lookup-table-based architecture is extremely efficient: it is capable of supporting up to two synapses per Configurable Logic Block (CLB). I n addition, the architecture is simple to implement, self-contained (weights are stored directly in the synapse), and scales easily across multiple chips. 189 0-8186-5490-2/94 $03.00 0 1994 IEEE

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This paper describes how the massive parallelism of the rapidly reconfigurable Xilinx XC6216