FPGA based string matching for network processing applications

Design and Implementation of NIDS String Matching Based on SOPC

“…We implemented a simple software string search test program using the GNUC library's hsearch function. The test program was run on a 1 GHz PowerPC computer and timed for just the search process, and the results are shown in Table 1 [7]. Table 1 The results of Software implementation As the table shows, the hardware implementation performs the search much faster-in fact nearly two orders of magnitude faster.…”

A bit-parallel algorithm for searching multiple patterns with various lengths

“…Work [13] GeForce GTX 480 30 n/a 50,000 20 Oh [31] GeForce GTX 480 3-15 3,180 34,915 n/a Zha [8] Tesla GT 200 9 904 33 17 Tumeo [12] Four Tesla C2050 12-48 100 190,000 16 Tumeo [9] Two Xeon X5560 3-20 100 190,000 16 AC-opt [17] Cray XMT 28 100 190,000 16 AC-opt [16] Cell/B.E. 3-4.5 4 20,000 8 Schatz [6] GeForce 8800 GTX 0.4-0.5 1* 312,500 800 Michailidis [15] FPGA 0.1 30 1 1,024 Singaraju [32] FPGA 3 n/a 1,237 13 *: 1 base pair = 2 bits complexity of the SSEF algorithm ranges from O(nm) to O(n/m) according to preprocessing effects, where n is the length of the text and m is that of the pattern.…”

NetStage/DPR: A self-reconfiguring platform for active and passive network security operations

“…Today, solutions capable of processing 10+ Gb/s are widely available. Katashita et al propose an integrated solution for packet inspection and filtering on a single FPGA [11], while Singaraju et al focus on string matching implementations for deep packet inspection [12].…”