FPGA-based training of convolutional neural networks with a reduced precision floating-point library

DiCecco, Roberto; Sun, Lin; Chow, Paul

doi:10.1109/fpt.2017.8280150

Cited by 15 publications

(7 citation statements)

References 4 publications

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“…FPGAs allow for faster development time and therefore are often used to explore various new research areas for CNNs, such as low-precision and binary networks [14,59], novel training regimes [15], and model compression through weight pruning or novel CNN structures [21,16]. In Section 7, we validate the performance of our filter matrix packing algorithm with an FPGA implementation.…”

Section: Asic and Fpga Accelerators For Cnnsmentioning

confidence: 99%

Packing Sparse Convolutional Neural Networks for Efficient Systolic Array Implementations

Kung

McDanel

Zhang

2019

Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Syst

125

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This paper describes a novel approach of packing sparse convolutional neural networks for their efficient systolic array implementations. By combining subsets of columns in the original filter matrix associated with a convolutional layer, we increase the utilization efficiency of the systolic array substantially (e.g., 4x) due to the increased density of nonzeros in the resulting packed filter matrix. In combining columns, for each row, all filter weights but one with the largest magnitude are pruned. We retrain the remaining weights to preserve high accuracy. We demonstrate that in mitigating data privacy concerns the retraining can be accomplished with only fractions of the original dataset (e.g., 10% for CIFAR-10). We study the effectiveness of this joint optimization for both high utilization and classification accuracy with ASIC and FPGA designs based on efficient bit-serial implementations of multiplier-accumulators. We present analysis and empirical evidence on the superior performance of our column combining approach against prior arts under metrics such as energy efficiency (3x) and inference latency (12x).

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Section: Asic and Fpga Accelerators For Cnnsmentioning

confidence: 99%

Packing Sparse Convolutional Neural Networks for Efficient Systolic Array Implementations

Kung

McDanel

Zhang

2019

Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Syst

125

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“…Recently, High-Level Synthesis libraries for supporting custom floating-point precision have been researched. These libraries are easy to use and portable compared to RTL approaches [56][57][58].…”

Section: B Reduced Precision Toolsmentioning

confidence: 99%

“…DiCecco et al [56] propose a custom-precision floatingpoint library (CPFP [59]) for High-Level Synthesis, and they evaluate it on a small convolution neural network. While the custom floating-point IP employs fewer resources than single precision, the FPGA design has a lower throughput than the CPU.…”

Section: B Reduced Precision Toolsmentioning

confidence: 99%

Reduced-Precision Acceleration of Radio-Astronomical Imaging on Reconfigurable Hardware

et al. 2022

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Radio telescopes produce large volumes of data that need to be processed to obtain high-resolution sky images. This is a complex task that requires computing systems that provide both high performance and high energy efficiency. Hardware accelerators such as GPUs (Graphics Processing Units) and FPGAs (Field Programmable Gate Arrays) can provide these two features and are thus an appealing option for this application. Most HPC (High-Performance Computing) systems operate in double precision (64-bit) or in single precision (32-bit), and radio-astronomical imaging is no exception. With reduced precision computing, smaller data types (e.g., 16-bit) are used to improve energy efficiency and throughput performance in noise-tolerant applications. We demonstrate that reduced precision can also be used to produce high-quality sky images. To this end, we analyze the gridding component (Image-Domain Gridding) of the widely-used WSClean imaging application. Gridding is typically one of the most time-consuming steps in the imaging process and, therefore, an excellent candidate for acceleration. We identify the minimum required exponent and mantissa bits for a custom floating-point data type. Then, we propose the first custom floating-point accelerator on a Xilinx Alveo U50 FPGA using High-Level Synthesis. Our reduced-precision implementation improves the throughput and energy efficiency of respectively 1.84x and 2.03x compared to the single-precision floating-point baseline on the same FPGA. Our solution is also 2.12x faster and 3.46x more energy-efficient than an Intel i9 9900k CPU (Central Processing Unit) and manages to keep up in throughput with an AMD RX 550 GPU.

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“…Much FPGA-based work focuses on Convolutional Neural Network (CNN) acceleration to meet the challenges of computing resources and energy consumption on CNN. The authors of [9][10][11][12] proposed to accelerate CNN on FPGA using simplified numerical precision to save chip resource consumption. The authors of [13,14] proposed CNN architecture implemented in FPGA with the Winograd algorithm to reduce the complexity of convolution operation and accelerate the computation process.…”

Section: Related Workmentioning

confidence: 99%

An FPGA-Based LSTM Acceleration Engine for Deep Learning Frameworks

et al. 2021

Electronics

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Over the past two decades, Long Short-Term Memory (LSTM) networks have been used to solve problems that require modeling of long sequence because they can selectively remember certain patterns over a long period, thus outperforming traditional feed-forward neural networks and Recurrent Neural Network (RNN) on learning long-term dependencies. However, LSTM is characterized by feedback dependence, which limits the high parallelism of general-purpose processors such as CPU and GPU. Besides, in terms of the energy efficiency of data center applications, the high consumption of GPU and CPU computing cannot be ignored. To deal with the above problems, Field Programmable Gate Array (FPGA) is becoming an ideal alternative. FPGA has the characteristics of low power consumption and low latency, which are helpful for the acceleration and optimization of LSTM and other RNNs. This paper proposes an implementation scheme of the LSTM network acceleration engine based on FPGA and further optimizes the implementation through fixed-point arithmetic, systolic array and lookup table for nonlinear function. On this basis, for easy deployment and application, we integrate the proposed acceleration engine into Caffe, one of the most popular deep learning frameworks. Experimental results show that, compared with CPU and GPU, the FPGA-based acceleration engine can achieve performance improvement of 8.8 and 2.2 times and energy efficiency improvement of 16.9 and 9.6 times, respectively, within Caffe framework.

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FPGA-based training of convolutional neural networks with a reduced precision floating-point library

Cited by 15 publications

References 4 publications

Packing Sparse Convolutional Neural Networks for Efficient Systolic Array Implementations

Packing Sparse Convolutional Neural Networks for Efficient Systolic Array Implementations

Reduced-Precision Acceleration of Radio-Astronomical Imaging on Reconfigurable Hardware

An FPGA-Based LSTM Acceleration Engine for Deep Learning Frameworks

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