2012
DOI: 10.1016/j.epsr.2012.04.003
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FPGA based variable frequency AC to AC power conversion

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Cited by 10 publications
(11 citation statements)
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“…The output voltage vo, output current io, and source input current iin waveforms, when the SSMC is connected to an RL load of 100 normalΩ + 15 mH, are shown in Figures 12–14, respectively. It can be recognized that the methods of previous studies 31–36 provide output voltage spikes at each switching cycle due to the lack of RL load freewheeling path when the PWM signal is low, as discussed earlier. Therefore, the methods of previous studies 31–36 cannot be used with adequate RL loads without the use of some external dissipative circuits, such as a clamp circuit.…”
Section: Simulation Studymentioning
confidence: 99%
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“…The output voltage vo, output current io, and source input current iin waveforms, when the SSMC is connected to an RL load of 100 normalΩ + 15 mH, are shown in Figures 12–14, respectively. It can be recognized that the methods of previous studies 31–36 provide output voltage spikes at each switching cycle due to the lack of RL load freewheeling path when the PWM signal is low, as discussed earlier. Therefore, the methods of previous studies 31–36 cannot be used with adequate RL loads without the use of some external dissipative circuits, such as a clamp circuit.…”
Section: Simulation Studymentioning
confidence: 99%
“…It is clear that even with a clamp circuit, the methods of previous works [31][32][33][34][35][36] still show voltage spikes when the PWM signal is low. Therefore, the resistance of R cl should decrease to eliminate the voltage spikes when the control methods of in previous studies [31][32][33][34][35][36] F I G U R E 1 8 The influence of clamp circuit components on the SSMC performance. (A) The effect of the clamp resistor value on the source current rms value and amplitude of voltage spikes.…”
Section: Case Study 3: Operation Under Rl Load With a Clamp Circuitmentioning
confidence: 99%
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“…During this interval, the grid voltage, V grid passing through L & C acts as input voltage, V CYCLO_OUT to the BDCC in reverse mode. The grid frequency voltage is converted to HFAC voltage in this mode by operating the BDCC in reverse mode [12][13]. In BDCC as shown in Fig.1, when the switches D 1 and D 2 are in ON state, the grid current flows through the path, grid-D 2 -HFT secondary terminals -D 1 -grid.…”
Section: Mode 3: Grid-ev Reverse Mode Operation Of the Proposed Ev Bamentioning
confidence: 99%