FPGA design and implementation of Direct Matrix Inversion based on steepest descent method

Sarraf, Élie; Ahmed-Ouameur, Messaoud; Massicotte, Daniel

doi:10.1109/mwscas.2007.4488771

Cited by 2 publications

(2 citation statements)

References 7 publications

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“…Finally, some authors proposed FPGA implementations of matrix multiplication or inversion, using different strategies [23,24,25]; the Parallel input/Multiple Output strategy proposed in this last paper, is very similar to our systolic array architecture.…”

Section: State Of the Art And Motivationmentioning

confidence: 99%

FPGA design of EKF block accelerator for 3D visual SLAM

Tertei

Piat

Devy

2016

Computers & Electrical Engineering

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International audienceThis paper deals with the evaluation of a dedicated architecture to be integrated into an embedded system typically mounted on a micro-aerial vehicle or on smart devices held by an operator. This system performs an Extended Kalman Filter (EKF) based visual odometry (VO) algorithm. An efficient hardware architecture conceived as a systolic array co-processor for EKF loop acceleration is presented. Due to severe limitations in terms of power consumption, real-time performance and physical characteristics of the system (i.e. compactness and weight), this algorithm is implemented entirely as a System On a programmable Chip (SoC) on the Zynq-7020 device. This heterogeneous (processor with reconfigurable hardware) platform consumes less power than a standard microprocessor and provides powerful parallel data processing capabilities: applying hardware/software (hw/sw) co-design allows real-time throughput with a very low power-per-feature rate

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Section: State Of the Art And Motivationmentioning

confidence: 99%

FPGA design of EKF block accelerator for 3D visual SLAM

Tertei

Piat

Devy

2016

Computers & Electrical Engineering

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“…Gradient descent algorithms [12,19,20] are a family of methods based on an iterative convergence towards the solution of the system, where the step size for each iteration is taken in the direction of the gradient of the function in Eq. 3.…”

Section: Iterative Gradient Algorithmmentioning

confidence: 99%

Iterative-Gradient Based Complex Divider FPGA Core with Dynamic Configurability of Accuracy and Throughput

López‐Martínez

Castillo-Sánchez

Entrambasaguas

et al. 2010

J Sign Process Syst

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A field programmable gate array (FPGA) implementation of a highly configurable complex divider is presented, based on an iterative gradient algorithm. The proposed architecture allows to configure both the accuracy and the throughput of the division operation, which makes it suitable for diverse applications with different requirements. Results show how various throughputs can be achieved under different maximum error and iteration limit configurations. Besides, the resource occupation is considerably small, compared with previous solutions.

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FPGA design and implementation of Direct Matrix Inversion based on steepest descent method

Cited by 2 publications

References 7 publications

FPGA design of EKF block accelerator for 3D visual SLAM

FPGA design of EKF block accelerator for 3D visual SLAM

Iterative-Gradient Based Complex Divider FPGA Core with Dynamic Configurability of Accuracy and Throughput

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